Cisco Technology, Inc.

Avago Technologies International Sales Pte. Limited

Adaptec, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Surendra Anubolu

Mohan V Kalkunte

James P Rivers

Sachin Prabhakarrao Kadu

Stewart Findlater

Laxminarasimha Rao Kesiraju

David Hsi-Chen Yen

Hiroshi Suzuki

Charles Troper Yager

Amar Chand Amar

Rochan Sankar

Bradley D Erickson

Stephen Francis Scheid

Sandeep Arvind Patel

Paul Norwood Booth

Andrew Michael Robbins

Rajesh Ekras Bawankule

Jacqueline Irene Humfeld

Samuel C Chih

Jianyun Zhou

The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.

Power throttle for network switches

The disclosed systems and methods provide weighted cost multipath for packet processing devices. A method includes receiving a network packet for routing through one of a number of paths of a network switch device. The method also includes selecting, via a first function applied to the network packet, a record from a plurality of records corresponding to the number of paths, wherein each of the plurality of records includes a threshold, a first routing index, and a second routing index. The method also includes determining, via a second function applied to the network packet, a routing value within a predefined range of values. The method also includes choosing, from the selected record, the first routing index or the second routing index based on whether the routing value meets the threshold of the selected record. The method also includes routing the network packet based on the chosen routing index.

Weighted cost multipath packet processing

A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic.

Flexible flow table with programmable state machine

A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.

Scalable low-latency mesh interconnect for switch chips

A method for managing recirculation path traffic in a network node comprises monitoring an input packet stream received at an input port of the network node and monitoring a recirculation packet stream at a recirculation path of the network node. A priority level associated with individual packets of the monitored input packet stream is detected and low priority packets are stored in a virtual queue. The method also includes determining an average packet length associated with packets of the monitored recirculation packet stream. The method further comprises queuing one or more of the low priority packets or the recirculation packets for transmission based on the average packet length and a weighted share schedule.

Flexible recirculation bandwidth management

Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values associated with original lengths of the bit messages before the CRC values are transmitted or forwarded with the bit messages to recipients.

Techniques for generating cyclic redundancy check (CRC) values

An Interchangeable Standard Port or Stack Port (ISPSP) uses a standard physical connector such as an RJ-45 or SFP. The ISPSP automatically detects whether it is connected to a standard port, such as a 1000BaseT, or whether it is connected to another ISPSP stacking port. This automatic detection can be done through hardware or software. Once the auto-detection is complete the routing platform will automatically configure the ISPSP port for standard 1 Gbps bit rate and framing, or for stacking, e.g., 2.5 Gbps bit rate, and framing.

Interchangeable standard port or stack port

A technique for allocating stack bus bandwidth based on the offered load of each stack member coupled to the stacking bus allocates access opportunities to the stack bus based on the ratio of the offered loads of the coupled stack members.

Offered load fairness in a stack

A ring access system, for use in system having a plurality of routing platforms coupled by redundant rings, that allows access to either ring when a token is received at a first ring if all outstanding locally-sourced data has been stripped from the second ring.

System and method for balancing rings coupling routing platforms

According to the present invention, a function timer is started whenever the PCI bus is granted to the function that did not access the PCI bus prior to the last bus idle state. The timer counts down to zero and waits until another function requests the PCI bus. During the time the timer is not zero, the current function will have the highest priority. Even if a PCI bus disconnect signal or retry signal forces the current function to deassert the request signal and start the request again, the current function is guaranteed to win the arbitration among the multiple contenders within the multi-function device. Since during the time slot, the same function will the granted access to the PCI bus, the next request will most likely be readily available from the PCI bridge's buffer which has additional data stored in anticipation for the next request. The use of the PCI bridge's buffer will maximize the system memory bus usage while increasing the PCI bus throughput. The time slot based arbitration according to the present invention rotates the priority to the other requesting function after the predetermined time expires which limits the latency for all the functions.

Timer based arbitrations scheme for a PCI multi-function device

The present invention provides the new capability to change PCI configuration registers. For example, the present invention allows programs, such as operating systems and device drivers, which are typically programmed to only look to the device ID, without looking to the subsystem ID, to read the subsystem ID when appropriate. If the programs do not read the subsystem ID register, then when appropriate, the full or partial content of the subsystem ID is copied into the device ID register.

Method and system for changing peripheral component interconnect

A computer system includes a number of storage elements encoded with space selection instructions and at least one current-space storage element that together allow a computer to address a larger number of devices than allowed by a limited number of address terminals on the computer. Specifically, the current-space storage element is encoded with a space-selection signal that indicates a 'current' address space, i.e. which one of a number of mutually exclusive address spaces is currently accessed. The space-selection signal can be changed by any device using a data bus to store signals indicative of a new address space as the 'current' address space in the current-space storage element. The current-space storage element is included in a first device that can be accessed by the computer at any time by driving a signal active on a high address line of an address bus. When the signal on the high address line is inactive, the computer accesses one of a number of second devices that are located in mutually exclusive address spaces, as indicated by the current-space storage element's signal.

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Fremont, CA, United States of America

Surendra Anubolu