Texas Instruments Corporation

Other

Array Microsystems, Inc.

Surendar S Magar

Edward R Caudel

Jerald G Leach

Kevin C McDonough

James F Potts

Antony W Leigh

Wanda K Gass

Gary L Swoboda

L Ray Simar, Jr

Daniel L Essig

Richard D Simpson

Gerry C Lui Kuo

Michael E Fleming

L Ray Simar Jr

Raul A Aguilar

A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Device for digital signal processing

A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Method of signal processing by contemporaneous operation of ALU and

Microcomputer for digital signal processing having on-chip memory and

Microcomputer system for digital signal processing

Modem employing digital signal processor

A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0- to -15 bit shifter with sign extension.

A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data buses (P-Bus and D-Bus) in special circumstances. The internal buses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Microcomputer system for digital signal processing having external

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

Data processing device with multiple on-chip memory buses

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

Data processing device with improved direct memory access

A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, the application of members of a signal array to be processed and the removal of the members of a processed signal array from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and the associated memory units. The control apparatus permits the digital signal processing device and associated memory units to operate in a normal mode where a predetermined processing operation is performed on the members of a signal array, a recursive mode where a series of operations are performed on a signal array by a single digital signal processing unit, and a sequential mode where a series of processing operations are performed on a signal array using a by plurality of digital signal processing units coupled in a series arrangement. The control apparatus has provision for automatic accommodation of predetermined latency in the signal member path, resulting from pipelined computation and from pipelined memory accesses, as well as accommodating preselected signal array sizes and preselected signal array overlap.

Apparatus and method for flexible control of digital signal processing

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microprocessor has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxillary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxillary arithmetic logic unit thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

Data processing device with multiple on chip memory buses

A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fitch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program memory may be a RAM and this additional RAM may be configured as either program or data memory space. The processor may operate with all off-chip program memory and a large on-chip data memory, or with program execution from on-chip RAM (downloaded from off-chip program memory) using a block move instruction. A repeat instruction is used to save program space when using block-move, or multiply instructions as needed for digital filters or the like.

Microprocessor with block move instruction

A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. A multiplier circuit produces a single state multiply function separate from the ALU. One input to the ALU passes through a full-width shifter with sign extension. The on-chip program memory is a RAM which may be configured as either program or data memory space. The processor may operate will all off-chip program memory and a large on-chip data memory, or with program execution from on-chip RAM (downloaded from the off-chip program memory) using a block move instruction. A repeat instruction is used to save program space when using block-move, or when using multiply instructions as needed for digital filters or the like.

Microprocessor with repeat instruction

A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes. Alternatively, the internal data RAM may be disabled and an external RAM used, for which a three-state or four-state instruction execution sequence is established instead of one per state to allow an operand to be transferred in on the data bus and high and low words of the accumulator transferred out; this node is very useful for checking ALU operations not otherwise accessible off-chip.

Growing community of inventors

Houston, TX, United States of America

Surendar S Magar