Arm Limited

Oracle International Corporation

Suraj Sudhir

Yuan C Chou

Rune Holm

Jayavarapu Srinivasa Rao

Jens Olson

A computer-implemented method, performed in a neural processing system comprising control processor circuitry and arithmetic logic circuitry, of performing a convolution between an input feature map (IFM) and convolutional filter data, resulting in an output feature map (OFM). The method includes, obtaining in the control processor circuitry, dimensional characteristic parameters relating to dimensions of input work batch data arrays and positional characteristic parameters relating to positions of feature map content within the input work batches. The method also includes, in the arithmetic logic circuitry, performing convolutions between the input work batches, generated from the IFM based on the dimensional characteristic parameters and the positional characteristic parameters, and work batch filter data arrays corresponding to the filter to produce a plurality of output work batch data arrays. The plurality of output work batches are combined to generate an OFM.

Neural processing system

A computer-implemented method of providing a filter (F) in a neural processing unit comprises: receiving input corresponding to target dimensions (X, Y) of the filter; receiving input corresponding to sub-filter dimensions (X', Y&#x2032;) of each of a plurality of sub-filters (SF) implementable in the neural processing unit; and defining the filter (F) as a combination of the plurality of sub-filters (SF), the combination having dimensions that equate to the target dimensions (X, Y), and wherein the sub-filter dimensions (X&#x2032;, Y&#x2032;) of at least two of the sub-filters in the combination are unequal.

Neural processing filter

The disclosed embodiments relate to a method for controlling prefetching in a processor to prevent over-saturation of interfaces in the memory hierarchy of the processor. While the processor is executing, the method determines a bandwidth utilization of an interface from a cache in the processor to a lower level of the memory hierarchy. Next, the method selectively adjusts a prefetch-dropping high-water mark for occupancy of a miss buffer associated with the cache based on the determined bandwidth utilization, wherein the miss buffer stores entries for outstanding demand requests and prefetches that missed in the cache and are waiting for corresponding data to be returned from the lower level of the memory hierarchy, and wherein when the occupancy of the miss buffer exceeds the prefetch-dropping high-water mark, subsequent prefetches that cause a cache miss are dropped.

Growing community of inventors

Santa Clara, CA, United States of America

Suraj Sudhir