Globalfoundries Inc.

University of Texas System

Suraj Kumar Patil

Min-Hwa Chi

Ajey Poovannummoottil Jacob

Keith Howard Tabakman

Zhiguo Sun

Katsunori Onishi

Chih-Chiang Chang

Pei Liu

Zeynep Celik-Butler

Donald Philip Butler

Garo Jacques Derderian

Jagar Singh

Huang Liu

Viraj Yashawant Sardesai

Vimal Kumar Kamineni

Uzodinma Okoroanyanwu

Scott Beasor

Huy Cao

Hui Zhan

Wen-Pin Peng

Mitsuhiro Togo

SherJang Singh

Pawitter J S Mangat

Sabarinath Jayaseelan

Obert R Wood

A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Integration scheme for gate height control and void free RMG fill

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SiGesubstrate; forming a conformal SiN, SiOCNlayer over side and bottom surfaces of the first trenches; filling the first trenches with SiO; forming a first mask over portions of the Si, Ge, III-V, or SiGesubstrate; removing exposed portions of the Si, Ge, III-V, or SiGesubstrate, forming second trenches; forming III-V, III-VM, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VM, or Si nanowires and intervening first trenches; removing the SiOlayer, forming third trenches; and removing the second mask.

Heterogeneous integration of 3D SI and III-V vertical nanowire structures for mixed signal circuits fabrication

Structures for a field-effect transistor and methods for forming a field-effect transistor. The structure includes a gate structure having a sidewall and a sidewall spacer arranged adjacent to the sidewall of the gate structure. The sidewall spacer includes an energy removal film material and one or more air gaps in the energy removal film material.

Integration of gate structures and spacers with air gaps

Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Programmable via devices with metal/semiconductor via links and fabrication methods thereof

A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Structure and method for capping cobalt contacts

Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

Method, apparatus, and system for E-fuse in advanced CMOS technologies

One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

Methods of forming MIS contact structures on transistor devices

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SiGesubstrate; forming a conformal SiN, SiOCNlayer over side and bottom surfaces of the first trenches; filling the first trenches with SiO; forming a first mask over portions of the Si, Ge, III-V, or SiGesubstrate; removing exposed portions of the Si, Ge, III-V, or SiGesubstrate, forming second trenches; forming III-V, III-VM, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-VM, or Si nanowires and intervening first trenches; removing the SiOlayer, forming third trenches; and removing the second mask.

Heterogeneous integration of 3D Si and III-V vertical nanowire structures for mixed signal circuits fabrication

A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

Semiconductor structure with anti-efuse device

Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating integrated circuits includes forming a gate dielectric overlying a substrate, and forming a base work function layer that includes tungsten overlying the gate dielectric. The base work function layer overlies the gate dielectric in a first and second region, where the first region is one of a pFET region or an nFET region and the second region is the other of the pFET region or the nFET region. A mask is formed over the first region, and then the second region is exposed. A work function value of the base work function layer in the second region is altered to produce a modified work function layer. The mask is removed from the over the first region, and a gate electrode is formed overlying the base and modified work function layers.

Integrated circuits with replacement metal gates and methods for fabricating the same

Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

Programmable devices with current-facilitated migration and fabrication methods

Method, apparatus, and system for e-fuse in advanced CMOS technologies

Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

Growing community of inventors

Ballston Lake, NY, United States of America

Suraj Kumar Patil