Massachusetts Institute of Technology

Sync Computing Corp.

Suraj Deepak Bramhavar

Jeffrey Chou

Paul William Juodawlkis

Cheryl Marie Sorace-Agaskar

Boris G Kharas

Marin Soljacic

George Barbastathis

Steven G Johnson

Jeffrey G Bernstein

Jeffrey Scott Herd

Erica Lin

Jamison Sloan

Josue Lopez

Siddhartha Ghosh

Samuel Kim

Titash Rakshit

William D Herzog

Reuel Bennett Swint

Christopher Roberts

Jason Plant

Christopher A D Roeser

Luna Xu

Marco Montes De Oca

A system including digital oscillators and at least one programmable interconnect is described. The programmable interconnect(s) provide weights for and selectably couples at least a portion of the digital oscillators. The digital oscillators and the programmable interconnect(s) form an optimization processing unit (OPU). A system for performing reversible logic is also described. The system includes digital oscillators coupled to perform a logic operation and an error correction unit coupled to the digital oscillators. The error correction unit is configured to sample states of the digital oscillators, detect error(s) in the states, and tune connection coefficient(s) between the oscillators in response to detecting the error(s).

Optimization processing unit utilizing digital oscillators

A method of efficiently executing a plurality of processes is described. The method generates, using a predictor, operating constraints for the processes. An operating constraint of the operating constraints is for each process of the processes. The method evaluates possible operating points for each process consistent with the operating constraints and according to a cost function for the processes. The method also determines an operating point for each process based on the evaluating.

Automated globally optimized resource allocator and scheduler

A method of assigning processing resources is described. The method includes receiving an application and analyzing the application to determine an expected run time use of the processing resources. At least a portion of the processing resources are assigned to the application based on the expected run time use of the processing resources. A computing system architecture including a processing resource pool, an interface, and a special purpose optimization coprocessor is also described. The interface receives an application to be executed. The special purpose optimization coprocessor receives information about the application and the processing resource pool and outputs an allocation scheme for allocating tasks of the application to the processing resource pool.

Real time scheduling using expected application resource usage

An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electronic components and compatible with traditional integrated circuit technologies. Each LC oscillator, or node, in the network can be coupled to each other node in the array with a multiply and accumulate crossbar array or optical interconnects. When implemented with four nodes, the system performs with single-run ground state accuracies of 98% on randomized MAX-CUT problem sets with binary weights and 84% with five-bit weight resolutions. The four-node system can obtain solutions within five oscillator cycles with a time-to-solution that scales directly with oscillator frequency. A scaling analysis suggests that larger coupled oscillator networks may be used to solve computationally intensive problems faster and more efficiently than conventional algorithms.

All-to-all connected oscillator networks for solving combinatorial optimization problems

Techniques usable in optimization processing are described. A system includes an optimization processing unit (OPU). The OPU includes stochastic computing units and at least one programmable interconnect. Each of the stochastic computing units includes nodes and multiplication unit(s) configured to interconnect at least a portion of the nodes. The programmable interconnect(s) are configured to provide weights for and to selectably couple a portion of the stochastic computing units.

Optimization processing unit having subunits that are programmably and partially connected

An integrated optical beam steering device includes a planar Luneburg lens that collimates beams from different inputs in different directions within the lens plane. It also includes a curved (e.g., semi-circular or arced) grating coupler that diffracts the collimated beams out of the lens plane. The beams can be steered in the plane by controlling the direction along which the lens is illuminated and out of the plane by varying the beam wavelength. Unlike other beam steering devices, this device can operate over an extremely wide field of view&#x2014;up to 180&#xb0;&#x2014;without any aberrations off boresight. In other words, the beam quality is uniform in all directions, unlike with aplanatic lenses, thanks to the circular symmetry of the planar Luneburg lens, which may be composed of subwavelength features. The lens is also robust to misalignment and fabrication imperfections and can be made using standard CMOS processes.

Planar Luneburg lens system for two-dimensional optical beam steering

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

All electrical fully connected coupled oscillator Ising machine

The accelerometers disclosed herein provide excellent sensitivity, long-term stability, and low SWaP-C through a combination of photonic integrated circuit technology with standard micro-electromechanical systems (MEMS) technology. Examples of these accelerometers use optical transduction to improve the scale factor of traditional MEMS resonant accelerometers by accurately measuring the resonant frequencies of very small (e.g., about 1 &#x3bc;m) tethers attached to a large (e.g., about 1 mm) proof mass. Some examples use ring resonators to measure the tether frequencies and some other examples use linear resonators to measure the tether frequencies. Potential commercial applications span a wide range from seismic measurement systems to automotive stability controls to inertial guidance to any other application where chip-scale accelerometers are currently deployed.

Apparatus and methods for photonic integrated resonant accelerometers

Photonic integrated circuits (PICs) enable manipulation of light on a chip for telecommunications and information processing. They can be made with silicon and silicon-compatible materials using complementary metal-oxide-semiconductor (CMOS) fabrication techniques developed for making electronics. Unfortunately, most light sources are made with III-V and II-VI materials, which are not compatible with silicon CMOS fabrication techniques. As a result, the light source for a PIC is either off-chip or integrated onto the PIC after CMOS fabrication is over. Hybrid integration can be improved by forming a recess in the PIC to receive a III-V or II-VI photonic chip. Mechanical stops formed in or next to the recess during fabrication align the photonic chip vertically to the PIC. Fiducials on the PIC and the photonic chip enable sub-micron lateral alignment. As a result, the photonic chip can be flip-chip bonded to the PIC with sub-micron vertical and lateral alignment precision.

Hybrid integration for photonic integrated circuits

An accelerometer may comprise a proof mass, a first tether mechanically coupled to the side of the proof mass and to an anchor, and a ring resonator integrated with the tether to form a sensing tether. The ring resonator and the tether may be configured such that a strain sustained by the sensing tether causes a change of a resonance condition of the ring resonator. The accelerometer may comprise a wavelength locking loop configured to adaptively maintain a center frequency of the light energy at a resonant frequency of the sensing element, and a scale factor calibrator configured to stabilize a scale factor associated with the accelerometer. The accelerometer may further include a detection processor configured to receive the detection signal and produce an acceleration signal therefrom. The acceleration signal may correspond to an amount of change of the resonance condition with respect to a reference resonance condition.

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Arlington, MA, United States of America

Suraj Deepak Bramhavar