Freescale Semiconductor,inc.

Legerity, Inc.

Suraj Bhaskaran

Zheng Xu

Jason T Nearing

Richard G Collins

Paul B Rawlins

Michael D Snyder

Klas Magnus Bruce

Vijayakumaran Velayudhan Nair

Matt B Smittle

Shankar R Kozhumam

A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.

Techniques for tracing processes in a multi-threaded processor

A method of generating timestamped trace messages includes generating a trace message in response to an event at an instruction pipeline of a data processing device. If timestamping is enabled, timestamps are only included in the trace message only if a programmable condition is detected. For example, a timestamp can be included in the trace message if the amount of space used to store messages at a trace message buffer exceeds a watermark value. The condition that results in a timestamped trace message is programmable, and can be selected via a debug interface. Because timestamps are only included in trace messages when the programmable condition is satisfied, some trace messages will not include a timestamp, thereby reducing the amount of buffer space needed to store the trace messages.

Trace messaging device and methods thereof

In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.

Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors

A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the data acquisition operation has been identified, data corresponding to the configuration information is written to a data register. The data in the data register and the configuration information in the configuration register are formatted into the data acquisition message. The data acquisition message is sent to the external port of the data processing system.

Data acquisition messaging using special purpose registers

In its many aspects and variations, a method for accessing a peripheral memory from a processor is provided. The method comprises first initiating the access. Information is then written from the processor to an operational register in a processor memory to enable the peripheral memory. The processor then processes parallel instructions for a predetermined time during which the access occurs. When the access is over, the processor reads the operational register to disable the peripheral memory. In other aspects, an apparatus programmed to perform this method and a program storage medium encoded with instructions that, when executed by a computer, perform the method are provided.

Programmable memory based control for generating optimal timing to access serial flash devices

A system includes a detector, a first and second processor, and a reset circuit. The detector delivers a first signal in response to detecting a preselected condition, such as low battery voltage. The first processor receives the first signal and delivers an acknowledge signal indicating that the first processor will enter a reset mode of operation in response to receiving a reset signal. The second processor enters the reset mode of operation in response to receiving the first signal. The reset circuit delivers a reset signal to the first processor in response to receiving the first signal and the acknowledge signal so that the first processor is reset when it has acknowledged that it is ready to do so.

Method and apparatus for controlling reset operations

An apparatus is used to control a reset function of an electronic device. The apparatus includes a circuit adapted to monitor a system voltage level and deliver a control signal in response to the system voltage level falling below a first preselected value. A duration controller receives the control signal and delivers a first reset signal for a preselected duration of time after receiving the control signal. A voltage level controller receives the first reset signal, and delivers a second reset signal that persists until the system voltage rises above a second preselected magnitude.

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Austin, TX, United States of America

Suraj Bhaskaran