Taiwan Semiconductor Manufacturing Comp. Ltd.

Sunny Wu

Jong-I Mou

Jo Fei Wang

Chun-Hsien Lin

Po-Feng Tsai

Chin-Hsiang Lin

Chia-Tong Ho

Yen-Di Tsen

Andy Tsen

Keung Hui

Chih-Tien Chang

Mei-Sheng Zhou

Yu-Liang Lin

Henry Lo

Chia-Hung Huang

Hung-Jung Tu

Ai-Sen Liu

Francis Ko

Ching-Ya Wang

Jui-Long Chen

Ping-Hsu Chen

Ming-Yu Fan

Ping Chuang

Chin-Hsin Peng

Chien-Ling Huang

Chih-Sheng Shih

Wang Jo Fei

Chun Hsien Lin

Jill Wang

Hsin Kuan

Hsueh-Chang Wu

Mei-Seng Zhou

Kun-Ming Chen

Dung-Yian Hsieh

Hui-Ru Lin

I-Ching Chu

Monghsung Chuang

Fu-Min Huang

A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.

Method and system for tool condition monitoring based on a simulated inline measurement

An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.

Real-time calibration for wafer processing chamber lamp modules

The present disclosure provides various methods for tuning process parameters of a process tool, including systems for implementing such tuning. An exemplary method for tuning process parameters of a process tool such that the wafers processed by the process tool exhibit desired process monitor items includes defining behavior constraint criteria and sensitivity adjustment criteria; generating a set of possible tool tuning process parameter combinations using process monitor item data associated with wafers processed by the process tool, sensitivity data associated with a sensitivity of the process monitor items to each process parameter, the behavior constraint criteria, and the sensitivity adjustment criteria; generating a set of optimal tool tuning process parameter combinations from the set of possible tool tuning process parameter combinations; and configuring the process tool according to one of the optimal tool tuning process parameter combinations.

Systems and associated methods for tuning processing tools

A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.

Integrated circuit manufacturing tool condition monitoring system and method

An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Semiconductor processing dispatch control

A method of automatically determining process parameters for processing equipment includes processing at least one first substrate in the processing equipment at a first time; and processing at least one second substrate in the processing equipment at a second time. The method includes collecting data on process monitors for the at least one first substrate; and the at least one second substrate. The method includes receiving the data by a multiple-input-multiple-output (MIMO) optimization system. The method includes revising a sensitivity matrix, by a MIMO optimizer, using the data and an adaptive-learning algorithm, wherein the adaptive-learning algorithm revises the sensitivity matrix based on a learning parameter which is related to a rate of change of the processing equipment over time. The method includes determining a set of process parameters for the processing equipment by the MIMO optimizer, wherein the MIMO optimizer uses the revised sensitivity matrix to determine the process parameters.

Adaptive and automatic determination of system parameters

The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.

E-chuck with automated clamped force adjustment and calibration

A MIMO optimizer is used to identify tunable process parameters for processing equipment.

A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.

Device performance parmeter tuning method and system

System and method for implementing wafer acceptance test ('WAT') advanced process control ('APC') are described. In one embodiment, the method comprises performing an inter-metal (&#x201c;IM&#x201d;) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.

System and method for implementing wafer acceptance test ('WAT') advanced process control ('APC') with routing model

A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

Physical failure analysis guiding methods

System and method for implementing wafer acceptance test ('WAT') advanced process control ('APC') are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process.

System and method for implementing a wafer acceptance test ('WAT') advanced process control ('APC') with novel sampling policy and architecture

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Zhudong Town, Taiwan

Sunny Wu