Intel Corporation

Koninklijke Philips Corporation N.v.

Nxp B.v.

Sunny C Huang

Nhon Toai Quach

Jeen Miin

Dean A Mulla

Muthurajan Jayakumar

John Wai Fu

Frans Sijstermans

Rudolf H J Bloks

Stephen S Pawlowski

Peter D MacWilliams

Alper Ilkbahar

William S Wu

Michael Paul Corwin

Kornelis Antonius Vissers

David N Harris

James Nadir

Stuart E Sailer

Bindi A Prasad

Ching-Hua Chu

Jason C Stinson

Lakshmi Rao

Marcel J A Tromp

Huang Kuang Hu

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

Combined tag and data ECC for enhanced soft error recovery from cache tag errors

Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a second instruction. Individual operations within a multi-operation instruction can be selectively enabled and disabled, which is advantageous in many situations, including event handling and code debugging.

Dynamically controlling execution of operations within a multi-operation instruction

The invention is directed to techniques for managing a cache within a processor using one or more machine instructions. The machine instructions may perform one or more operations on the cache. For example, victimize instructions, allocate instructions, and pre-fetch instructions can be executed in the processor as part of cache management. Moreover, these various cache management instructions may be defined by one or more operands that specify memory addresses within main memory, rather than addresses or identifiers that define locations within the cache. For this reason, a programmer may invoke these cache management instructions to direct the management of the cache without knowing the specific location of data within the cache.

Cache management instructions

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

A cache memory includes a plurality of lines of memory and a plurality of cache coherency state registers. Each of the plurality of cache coherency state registers is associated with one of the plurality of lines of memory. Each of the plurality of cache coherency state registers further includes four elements having one of a first value and a second value to form a four bit code for a MESI Protocol. The four bit code provides a first set of codes having a minimum distance of two from every other code, and a second set of codes having a minimum distance of three from every other code. The first set of codes includes a first code representing an Invalid state, a second code representing a Shared state, and a third code representing an Exclusive state. The second set of codes includes a fourth code representing a Modified state.

Cache memory and system with partial error detection and correction of MESI protocol

A method and an apparatus for receiving partially error protected data. A transmission of a binary code is received. The binary code is selected from a first set of codes having a first minimum distance from every other code and a second set of codes having a second minimum distance from every other code. The second minimum distance is greater than the first minimum distance. A first single bit error in the transmission is detected if the transmission is a distance of one unit from one of the codes in the second set of codes.

Method and apparatus for partial error detection and correction of digital data

A system for processing caches misses includes a request miss buffer, secondary miss logic, and a request identifier buffer. When a request misses in a cache, information characterizing the request is provided to the request miss buffer and the secondary miss logic. The secondary miss logic determines whether the request may be merged with a pending bus transaction, and provides the request identifier buffer with a pointer to the request information. The pointer is stored at an entry associated with the pending bus transaction. For a load request, data returned by the bus transaction is routed to a targeted register, using the request information in the request miss buffer.

Method and apparatus for processing cache misses

A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply

Method and apparatus for performing bus operations in a computer system

An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal. Odd-numbered half-cycles begin with a domino gate of the second type controlled by the second clock signal, followed by domino gates of the first type controlled by the fourth clock signal.

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Cupertino, CA, United States of America

Sunny C Huang