Intel Corporation

Sunnhyuk Kimn

Roger A Golliver

Gautam B Doshi

Sivakumar Makineni

A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations

A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.

Growing community of inventors

Campbell, CA, United States of America

Sunnhyuk Kimn