Samsung Display Co., Ltd.

Sunkyu Son

Jae-Han Lee

Young-Il Ban

Taegon Kim

Sooyeon Kim

Wontae Kim

Sun-Koo Kang

Sujin Kim

Yanguk Nam

Inyong Hwang

Dong-Hyun Yeo

Byungkil Jeon

Myong-Bin Lim

OckJin Kim

Youngil Ban

Sunkoo Kang

Young-Ii Ban

Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.

Data integrated circuit including latch controlled by clock signals and display device including the same

A driving method of a display device includes sequentially outputting a plurality of eye tuning signals, receiving a plurality of checking information obtained from a data driving circuit, wherein the checking information indicates whether the data driving circuit is operating in response to each of the plurality of eye tuning signals, and selecting one optimal eye tuning signal among the plurality of eye tuning signals operating the data driving circuit on the basis of the checking information. Image signals are output on the basis of condition information of the optimal eye tuning signal.

Display device and method of tuning a driver

There is provided a display device including a power management integrated circuit outputting a driving voltage and a gamma voltage, a timing controller outputting an image data signal and a driving control signal, a data driver converting the image data signal to a data voltage signal based on the driving voltage, the gamma voltage, and the driving control signal, a power connecting portion connecting the power management integrated circuit and the data driver, a voltage detector detecting the driving voltage and the gamma voltage that are voltage-dropped in the power connecting portion, and outputting a feedback signal, and a power adjustor receiving the feedback signal and outputting a power control signal to the power management integrated circuit, and adjusting the driving voltage and the gamma voltage based on the power control signal.

Display device

A driving circuit includes a receiver configured to receive an image control signal comprising a data signal and a clock signal, separate the data signal from the clock signal and output the separated data and clock signals, a clock recovery unit generating a reference clock signal based on the clock signal and generating a plurality of multi-phase clock signals having different phases from that of the reference clock signal, an output clock generation unit outputting an output clock signal in synchronization with the clock signal and the plurality of multi-phase clock signals, and a data output unit driving a plurality of data lines with a data driving signal corresponding to the data signal in synchronization with the output clock signal, and the output clock generation unit outputs the plurality of multi-phase clock signals.

Driving circuit adjusting output timing of data driving signal according to positions of data lines and display apparatus including the same

A display device including: a display panel displaying an image based on first and second frames; a timing controller outputting a plurality of image signals for each of the first and second frames and outputting a test signal during a reset section; and a source driving chip outputting a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal. The reset section is arranged after the first frame and before the second frame, and the source driving chip blocks the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage.

Display device and source driver to automatically block data voltage output to dummy lines

A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.

Controller

Disclosed is a display apparatus including: a display panel including pixels connected with a plurality of gate lines and a plurality of data lines; a gate driver supplying gate signals to the gate lines; and a data driver supplying data voltages to the data lines. The data driver includes a temperature measurer generating a temperature signal of the data driver.

Display apparatus

A display device includes a first interconnection line, a first data driver, a second interconnection line, an electrostatic discharge (ESD) circuit, and a display panel. The first connection line transmits a data driving signal. The first data driver includes the first interconnection line and output a data signal based on the data driving signal. The second interconnection line passes through the first data driver and transmits a gate driving signal. The ESD) circuit in the first data driver and discharges static electricity transmitted through the second interconnection line. The first gate driver outputs a gate signal based on the gate driving signal transmitted through the second interconnection line. The display panel receives the data signal and the gate signal.

Display device having ESD circuit

A display driving circuit includes a digital-to-analog converter configured to convert a digital image signal to an analog image signal, and a buffer circuit configured to receive the analog image signal and to output an output signal to be applied to a data line, where the buffer circuit includes an input stage configured to receive the analog image signal and to output a first signal, a first output stage configured to receive a first voltage and a second voltage and to output the output signal, a second output stage configured to receive a third voltage and a fourth voltage and to output the output signal, and a selection circuit configured to apply the first signal from the input stage to the first output stage or the second output stage in response to a mode signal.

Display driving circuit, display apparatus having the same and method of driving the same

A liquid crystal display having data driving apparatus comprising first and second output switches, a charge sharing line, and first and second charge sharing switches. The first output switch switches an electrical connection between a first amplifier providing a positive gradation voltage and a first data line in response to a control signal. The second output switch switches an electrical connection between a second amplifier providing a negative gradation voltage and a second data line in response to the control signal. The first charge sharing switch switches an electrical connection between the first data line and the charge sharing line in response to the control signal. The second charge sharing switch switches an electrical connection between the second data line and the charge sharing line in response to the control signal.

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Suwon-si, South Korea

Sunkyu Son