International Business Machines Corporation

Sunit S Mahajan

Teodor Krassimirov Todorov

Richard Stephan Wise

Bachir Dirahoui

Iqbal Rashid Saraf

Scott R Stiffler

Diego A Hoyos

William L Nicol

Techniques for precisely controlling the composition of volatile components (such as sulfur (S), selenium (Se), and tin (Sn)) of chalcogenide semiconductors in real-time&#x2014;during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a S source(s) and a Se source(s); heating the S source(s) to form a S-containing vapor; heating the Se source(s) to form a Se-containing vapor; passing a carrier gas first through the S-containing vapor and then through the Se-containing vapor, wherein the S-containing vapor and the Se-containing vapor are transported via the carrier gas to a sample; and contacting the S-containing vapor and the Se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material. A multi-chamber processing apparatus is also provided.

Anneal techniques for chalcogenide semiconductors

A plasma processing apparatus for reactive ion etching a wafer includes a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p&#x2212; layer and an n+ layer. Both p&#x2212; and n+ layers have exposed peripheral edges. Also provided is an anode comprising the plasma, a cathode comprising the wafer chuck, and a gate comprising the peripheral edge of the n+ layer. A coating layer is formed on a portion of the peripheral edge of the n+ layer. The coating layer reduces charge flow to a portion of the semiconductor wafer below the coating layer.

Method of charge controlled patterning during reactive ion etching

Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion of the deep trench cavity is formed to expose a sidewall of the buried insulator layer. A protective layer is disposed on the sidewall of the buried insulator layer. Then, the cavity is extended into the bulk substrate. The protective layer prevents over etch of the buried insulator layer during this process. The protective layer is then partially removed, such that the semiconductor-on-insulator (SOI) layer sidewall is exposed. The trench is then filled with a conductive fill material, such as polysilicon. The protection of the buried insulator (BOX) layer allows the trenches to be placed closer together while reducing the risk of a short circuit due to over etch, thereby increasing circuit density and product yield.

Deep trench sidewall etch stop

A method of reactive ion etching a wafer includes providing a plasma processing tool having a wafer chuck within a chamber and an electrode creating a plasma above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p&#x2212; layer and an n+ layer. Both p&#x2212; and n+ layers have exposed peripheral edges during plasma etching to electrically form with the plasma processing tool during plasma etching a diode having an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge. The method includes controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer edge, and reactive ion etching the n+ layer while controlling the charge flow along the edge of the n+ layer.

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Somers, NY, United States of America

Sunit S Mahajan