Avago Technologies General IP (singapore) Pte. Ltd.

Samsung Sds America, Inc.

Sunil Srinivasa

Amaresh Virupanagouda Malipatil

Pervez Mirza Aziz

Shiva Prasad Kotagiri

Mohammad Shafiul Mobin

Vladimir Sindalovsky

Adam Benjamin Healey

Mark Trafford

Girish Kathalagiri Somashekariah

Abhishek Mishra

Aleksander Beloi

Sundeep Venkatraman

Mohamad Charafeddine

Luis Quintela

An approach for spending allocation, executed by one or more processors to provide one or more monetary output values in response to a request for determining spending allocation in a digital marketing channel, is provided. The approach fits one or more models to train a business environment simulator. The approach generates a supervised learning policy. The approach evolves a supervised learning policy into a distribution estimator policy by adjusting network weights of the supervised learning policy. The approach generates an optimized policy by evolving the distribution estimator policy through interaction with the business environment simulator. The approach determines a profit uplift of the optimized policy by comparing the optimized policy and the supervised learning policy. Further, in response to the optimized policy outperforming the supervised learning policy, the approach deploys the optimized policy in a live environment.

Spending allocation in multi-channel digital marketing

A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains

An apparatus for recovering a clock from a data signal includes an out-of-lock detector configured to detect when a receiver data clock has a frequency offset with respect to a transmitter data clock associated with the data signal, an out-of-lock counter configured to count out-of-lock conditions for the receiver data clock, and a loop filter configured to correct the frequency offset in the receiver data clock based at least in part on the count of out-of-lock conditions.

Out-of-lock based clock acquisition

Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a 'biased' bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.

IQ-skew adaptation for a symmetric eye in a SerDes receiver

A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.

Enhanced clock and data recovery acquisition in the presence of large frequency offsets

An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

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San Jose, CA, United States of America

Sunil Srinivasa