Lattice Semiconductor Corporation

Sunil Sharma

Venkatesan Rajappan

Mohan Tandyala

Amit Singh

Mohana Tandyala

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a method includes identifying a multiplexer in the design, identifying one or more irrelevant inputs for the multiplexer by, at least in part, decomposing the select logic into one or more select line binary decision diagrams corresponding to the one or more select lines, and generating a reduced multiplexer by eliminating the one or more irrelevant inputs from the multiplexer. The reduced multiplexer may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.

Multiplexer reduction for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.

Efficient constant multiplier implementation for programmable logic devices

Techniques are provided to assign a set/reset signal of a user design to global set/reset (GSR) resources of a programmable logic device (PLD). By assigning a set/reset signal of the user design to the GSR resources during synthesis and prior to mapping, configurable resources consumed by the design may be reduced. In one example, a method includes receiving a user design for a programmable logic device (PLD) that comprises a plurality of configurable resources and global set/reset (GSR) resources. The method also includes identifying a plurality of set/reset signals of the user design. The method also includes determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources. The method also includes assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement. Additional methods and related systems are also provided.

Early global set/reset signal determination for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The computer-implemented method also includes synthesizing the design into a plurality of PLD components. In the computer-implemented method, the synthesizing includes detecting an incrementer-multiplier operation in the design and merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.

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Fremont, CA, United States of America

Sunil Sharma