Institute for the Development of Emerging Architectures, L.l.c.

Intel Corporation

Hewlett-packard Company

Idea Corporation

Sunil Saxena

Jonathan Kent Ross

Koichi Yamada

Gary N Hammond

William R Bryg

Stephen G Burger

James O Hays

John M Kessenich

Achmed Rumi Zahir

Jerome C Huck

Prasad A Raje

Cary Coutant

Carol Thompson

The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.

Apparatus and method for a virtual hashed page table

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A &ldquo;short format&rdquo; page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single &ldquo;long format&rdquo; page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2 bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2 bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

Method and apparatus for calculating a page table index from a virtual address

A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.

Cover instruction and asynchronous backing store switch

A method and an apparatus for profile guided TLB's (translation look-aside buffer) and cache optimization in an operating system. A typical operating system has a working set of information for any application which is running at some time. This working set of information can be written out by the operating system in some section of the object file. Once this information is in the object file, it may be utilized by the operating system in various ways. The method and apparatus decreases TLB misses for the benchmarks, disables infrequently used pages from disturbing the caches, and provides better rates on caches. This and many other advantages of the invention allow an increased efficiency and optimization of a given operating system.

Profile guided TLB and cache optimization

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Sunnyvale, CA, United States of America

Sunil Saxena