Other

Sunil Papanchand Khatri

Nikhil Jayakumar

Sabyasachi Das

Timothy Kevin Griffin

Sheila Vaidya

According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.

Low power reconfigurable circuits with delay compensation

A method and routing device are provided for routing a datapath design. Regularity may be extracted among routing connections of the datapath design. A representative bit-slice may be selected and one representative net from each net cluster in the representative bit-slice may be routed. The route of each routed net in each net cluster may be propagated to a remaining routes in each net cluster.

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College Station, TX, United States of America

Sunil Papanchand Khatri