Motorola Corporation

Sunil P Khatri

Renny L Eisele

William C Moyer

William C Bruce

Roger S Countryman, Jr

A circuit die (10) has circuit modules (12a-12f). Adjacent the circuit modules (12a-12f) is a plurality of redundant circuits regions (14a-14i). Each of the redundant circuit regions (14a-14i) has one or more redundant circuits, such as redundant circuits (16k-16n). The redundant circuits (16k-16n) are identified and oriented via one of a binary, a ternary, or a quaternary circuit identifier comprised of symbols, such as symbols (18, 24, 44, and 56). The symbols (18, 24, 44, and 56) are capable of being lithographically defined in a small surface area and therefore minimize the surface area consumed by the redundant circuits regions (14a-14i). The redundant circuits (16k-16n) are preferably used by focused ion beam (FIB) equipment to replace, repair, or supplement various electrically functional portions of the circuit modules (12a-12f).

Circuit identifier for use with focused ion beam equipment

A CMOS driver circuit (20) has a high impedance driver (30) and a low impedance driver (36) connected to the near end of a transmission line (43). The output impedance of the high impedance driver (30) matches the characteristic impedance of the transmission line (43). As a digital signal from the CMOS driver circuit (20) transitions from one logic state to another, the low impedance driver (30) drives the transmission line (43) until a predetermined voltage before the signal reaches its steady state voltage. A sensing circuit (24) senses when the predetermined voltage is reached, and in response, provides a control signal to deactivate the low impedance driver (36). The high impedance driver (30) completes the signal transition. The high impedance driver (30) absorbs the reflected waves from the far end of the transmission line (43), reducing the effects of ringing, and increasing noise immunity.

Driver circuit with self-adjusting impedance matching

A data processing system (90) having a serial scan circuit (10). The serial scan circuit (10) has an address detector (12) for detecting and decoding M serially-provided address bits. Coupled to the address detector (12) is a clock generator (14) which is used for providing at least one derived clock signal. Coupled to the address detector (12) and the clock generator (14) is a serial scan chain (16) which is used to store N serially-provided data bits. A plurality of serial scan chains (10) is connected in a parallel configuration and used to form the data processing system (90). The M address bits and the N data bits are serially provided via a single conductor (24) in a time division multiplexed operation. Integrated circuit surface area is reduced by avoiding large address and data buses, and bus routing.

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Austin, TX, United States of America

Sunil P Khatri