Sun Microsystems, Inc.

Xerox Corporation

Sunil Nanda

Norman M Hayes

Pradeep S Sindhu

Jean-Marc Frailong

Rajiv N Patel

Richard D Trauben

In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n.sub.1 and n.sub.2 integer and floating point results per clock cycle respectively, where n.sub.1 and n.sub.2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache. The instruction control unit decodes the instructions, detects operands cascading from instruction to instruction, group instructions into instruction groups of at most m instructions applying a number of exclusion rules, and issuing the grouped instructions simultaneously to the integer and/or floating point unit for execution. The exclusion rules reflect the resource characteristics and the particular implementation of the pipelined processor. The instruction control unit also tracks the history of the instruction groups and uses the history in conjunction with the exclusion rules in forming the instruction groups.

Method and apparatus for grouping multiple instructions, issuing grouped

A method and apparatus for removing a page table entry from a plurality of translation lookaside buffers ('TLBs') in a multiprocessor computer system. The multiprocessor computer system includes at least two processors coupled to a packet-switched bus. Page table entries are removed from a plurality of TLBs in the multiprocessor computer system by first broadcasting a demap request packet on the packet-switched bus in response to one of the processors requesting that a page table entry be removed from its associated TLB. The demap request packet includes a virtual address and context information specifying this page table entry. Controllers reply to the demap request packet by sending a first reply packet to the controller that sent the original demap request packet to indicate receipt of the demap request packet. If a controller removes the page table entry from its associated TLB, that controller sends a second demap reply packet to indicate that the page table entry has been removed from its associated TLB.

Broadcast demap for deallocating memory pages in a multiprocessor system

In a sequential logic design having two domains, each having opposing clock edge for its flip-flops, an inter-domain latch is provided for establishing a controllable and observable boundary point for the two domains. The inter-domain latch comprises three multiplexors and three latches. The first multiplexor, the first latch, the second multiplexor, the second latch, the third latch and the third multiplexor are coupled serially. Additionally, the output of the first latch is by-passed to the third multiplexor. The latches either open when the clock pulse is low or when the clock pulse is high. The first and third latches are driven by the same clock pulses, and the second latch is driven by an inverted clock pulse. Scan vectors for the first and second domains are scanned in through the first and second multiplexors respectively. The outputs of the first and second domains are observed at the second latch and the third multiplexor respectively.

Inter-domain latch for scan based design

A method and apparatus for selecting an entry to be replaced in a translation lookaside buffer in a computer system. The translation lookaside buffer stores a plurality of entries of virtual-to-physical address translations with each entry having a used bit and a valid bit. The circuit comprises a validity circuit coupled to the valid bit of each entry for determining whether the entry is valid and if not, the validity circuit causes a first signal to be asserted; a use circuit coupled to the used bit of each entry and to the validity circuit for determining whether the entry is used when a control signal is present and if not, the use circuit asserts a second signal to the validity circuit, the asserted second signal causing the first signal to be asserted; a ripple circuit coupled to each entry, its previous entry and its next entry, the ripple circuit receiving the first signal from the validity circuit of each entry and a first FOUND signal from its previous entry, the ripple circuit outputting a second FOUND signal, the ripple circuit causing the second FOUND signal to be asserted when the first signal is asserted and the first FOUND signal is de-asserted, the ripple circuit causing the second FOUND signal to be asserted when the first FOUND signal is asserted, the second FOUND signal being input to the ripple circuit of its next entry, wherein an asserted second FOUND signal for an entry causes the second FOUND signal for its next entry to be asserted, such that an entry with an asserted second FOUND signal propagates the asserted second FOUND signal through its next consecutive entries.

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Los Altos, CA, United States of America

Sunil Nanda