Cypress Semiconductor Corporation

Sunil Kumar Koduru

Rajesh Manapat

Scott Latham

Cathal G Phelan

Scott Harmel

Embodiments of the present invention relate to an electronic device having programmable chip enable inputs in that each chip enable has a programmable assertion level, e.g., high or low. The device may be an integrated memory chip, e.g., SRAM device. On power up, a JTAG input port of the electronic device can be used to program a configuration register which contains bits for setting the assertion level of each chip enable input. The bits may be used to control respective multiplexers which select between a chip enable signal and its inverse. The chip enable signals may originate from a controller device. Regarding a memory device, the outputs of the multiplexers are coupled to chip enable signals of an integrated memory core. The pre-configurable chip selects comprise chip select pins which are individually configured to active-high or active-low configurations so that the number of selectable memory chips requires only a number of chip selects equal to the number of times a memory is doubled, plus one chip select.

Method for configuring chip selects in memories

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to a reference impedance. The second circuit may be configured to operate in (i) a first mode in response to a first state of a second control signal and (ii) a second mode in response to a second state of the second control signal. When the second circuit is in the first mode, an output impedance of the second circuit may be adjusted in response to the one or more first control signals and the one or more first control signals may be presented at a first input/output of the second circuit. When the second circuit is in the second mode, the output impedance of the second circuit may be adjusted in response to one or more third control signals received at a second input/output of the second circuit.

Master/slave method for a ZQ-circuitry in multiple die devices

A circuit generally comprising a memory and a logic circuit. The memory may comprise (i) a first section configured to (a) read and write data and (b) have a first configurable size and (ii) a second section configured to (a) read and write data independently of the first section and (b) have a second configurable size. The logic circuit may be configured to control the first configurable size and the second configurable size.

Method, architecture and circuitry for independently configuring a multiple array memory device

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to a reference impedance. The second circuit may be configured to operate in (i) a first mode in response to a first state of a second control signal and (ii) a second mode in response to a second state of the second control signal. When the second circuit is in the first mode, an output impedance of the second circuit may be adjusted in response to the one or more first control signals and the one or more first control signals may be presented at a first input/output of the second circuit. When the second circuit is in the second mode, the output impedance of the second circuit may be adjusted in response to one or more third control signals received at a second input/output of the second circuit.

A dual port memory comprising a memory array, a first address circuit, a second address circuit, a timing circuit, a first data circuit and a second data circuit. The memory array may be configured to (i) write information to a first port or (ii) read information from a second port in response to (i) one or more first timing signals and (ii) one or more second timing signals. The first address circuit may be configured to present one or more first control signals in response to one or more first address signals. The second address circuit may be configured to present one or more second control signals in response to one or more second address signals. The timing circuit may be configured to present the one or more first timing signals and the one or more second timing signals in response to the one or more first control signals and the one or more second control signals. The first data circuit may be configured to read or write information from the first port of the memory array. The second data circuit may be configured to read or write information from the second port of the memory array.

Dual port sram

A memory device (e.g., an SRAM) is configurable to be operated in an asynchronous or a synchronous mode in accordance with a value stored in a control register thereof. In addition to asynchronous and synchronous operating modes, additional features such burst mode operations, including asynchronous burst mode operations and/or synchronous burst mode operations (e.g., linear sequential and/or interleaved burst operations); the number of pipeline stages of an output path of the SRAM; and/or the number of data hold cycles for synchronous operation of the SRAM are configurable in accordance with additional values stored in the control register.

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Sunnyvale, CA, United States of America

Sunil Kumar Koduru