Intel Corporation

Sunil K Jain

Gregory P Chema

Kim Kee Chow

Greg P Chema

Yanli Zhang

Paul Winer

Akihiro Takagi

Systems and methods may involve minimizing interference when synchronization information is being transmitted from multiple sources. This may include receiving a trigger signal wherein the trigger signal includes a timing parameter to be used by a user device to synchronize with a content platform, and transmitting a synchronization signal having a transmitter identification and the timing parameter.

Providing timing information over a data link

Active Space separates the Left Frame from the Right Frame in a frame packing format. A source device is expected to transmit a constant pixel value. A sink device is expected to ignore all data received during the Active space regardless of the value. Embodiments of the present invention involve the Source device to embed intelligent information in the Active Space in lieu of the recommended fixed pixel value. Then the Sink device may read the embedded information from the Active Space, and infer the transition between the left frame and the right frame which is useful, for example, to synchronize eyewear.

Method and apparatus for making intelligent use of active space in frame packing format

Polarized 3D viewing systems inherently cut the viewing resolution in half. While 3D content looks of good quality, the quality of any co-existing 2D content in windowed mode on the same screen looks poor. Embodiments may be directed to modifying the 2D content in real time and presents the enhanced 2D content (i.e. 2D+) to each eye as if it was 3D content targeted at each of the left and right eyes separately. The 2D+ content quality thus appears much better than when viewing the original 2D content on a polarized screen through polarized eyewear.

2D quality enhancer in polarized 3D systems for 2D-3D co-existence

Embodiments are directed to adaptive stable image timing in stereoscopic 3D systems which may include maximizing the ratio of the Addressable Video time to a total time between two horizontal Sync pulses and minimizing the ratio of 'Addressable' Video time to a total time between two Vertical Sync pulses. As the resolution size of the display decreases, the ratio minimized gets even smaller, leading to longer stable image resulting in higher 3D viewing quality.

Method and apparatus for adaptive stable image timing in stereoscopic 3D systems

Method and apparaus for making intelligent use of active space in frame packing format

Techniques are described that can be used to provide color space conversion for images and video to a display color gamut space. Some techniques provide for accessing an sRGB gamut color table, determining a color conversion matrix based on the sRGB gamut color table and chromaticity values of RGBW primary and gamma stored in the display or associated with the display, applying color space conversion to the pixels for pixels using the color conversion matrix, and applying linear correction of pixels by applying a normalization factor to the color conversion matrix. In addition, some techniques provide analysis of content gamut with respect to display gamut in HSV space, adjustment in HSV space, and conversion back to RGB space before applying color space conversion.

Techniques for adapting a color gamut

Embodiments of the invention provide a flexible probe head that improves contact force and uniform mechanical contact pressure between the probe feature and an engaged bond pad. Flexible probe head is formed from a plurality of conductive wires embedded in a high frequency elastomer material. During wafer sort, the flexible probe head is in contact communication with die under test. The flexible probe head assumes the natural co-planarity of the surface of the die under test and sort interface unit.

Flexible head probe for sort interface units

An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from the pass setting until the sampling phase is outside the eye width of the received data. The sampling phase is then incremented in an opposite direction of the first direction starting again from the pass setting until the sampling phase is outside the eye width of the received data. The number of the sampling phase increments in the first direction is added to the number of the sampling phase increments in the opposite direction to characterize the eye width of the received data.

Eye width characterization mechanism

A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment in which the electronic device is to be tested. A virtual calibration of the virtual test environment may be performed, to more closely emulate the actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal that is applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. Based on that evaluation an adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.

Virtual test environment

A method of and an apparatus for designing a test environment and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. An adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.

Testing of a mixed signal electronic device, and evaluating of a test environment. A test driver applies an input test signal to the device. The response of the device is monitored on a differential monitoring device to obtain analog data and on a tester receiver to obtain digital data. The analog data and the digital data are processed, the processed data are compared and evaluated, and the device is evaluted. A virtual test environment is created emulating an actual test environment, and a virtual device emulating the actual device is created and is stimulated with an input test signal emulating an actual input signal. The response of the virtual device is monitored to obtain analog data and digital data. The analog data and the digital data are processed, the processed analog and digital data are compared and evaluated, and the virtual device is evaluated.

Method of and apparatus for testing a serial differential/mixed signal device

A method of and an apparatus for determining the correctness of the calibration of an automatic test arrangement and correcting errors in the automatic test arrangement. The electrical length is determined from the tester driver of the automatic test arrangement to the socket pin of the tester interface unit, from the tester driver to a grounding point of the device under test, from the tester driver to the tester interface unit, and with the tester interface unit output pin connected to ground by a shorting block from the tester driver through the shorting block ground. The difference between the first electrical length and the second electrical length is compared with the difference between the first electrical length and the third electrical length, and the result is evaluated to determine the correctness of the calibration of the automatic test arrangement.

Method of and apparatus for measuring the correctness of and correcting an automatic test arrangement

Tester derating factor (TDF) arrangements and methodologies providing improvements in semiconductor start-to-finish manufacturing arrangements, especially within DV testing and in the world of designing of devices and virtual simulation.

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Folsom, CA, United States of America

Sunil K Jain