Intel Corporation

Sunil Gupta

Rodney R Rozman

Reed Linde

Rich Fackenthal

Iredamola Dammy Olopade

Nicholas J Denler

Sulakshana Shyama Nath

Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each glitch-sensitive node, a circuit fanin cone is analyzed to look for circuit structures that can produce glitches. The integrated circuit design can be simulated and modified if the simulation indicates that a glitch would occur in the integrated circuit design.

Tool for glitch removal

A system, apparatus, method and article to encode, clock recover, and sample data bits are described. The apparatus may include a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input. The first clock input to receive an encoded signal from a single-wire. The encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit. The pulsed digital module to capture an edge of the encoded signal at the first clock input in accordance with a logic level coupled to the first data input. A delay module comprising a delay input is coupled to the data output and a delay output is coupled to the reset input. The delay module to delay the captured edge by a predetermined period and to generate a delay signal from the delay output after the predetermined period. The pulsed digital module is to generate a first clock edge of the sampling clock at the data output after the predetermined period. An apparatus, system, and method to embed a sampling clock signal via an encoded signal comprising n bits and to transmit the encoded signal to a single-wire as a serial bit sequence of n bits. The encoded signal represents a logic bit having an encoding clock period T. Other embodiments are described and claimed.

Encoding, clock recovery, and data bit sampling system, apparatus, and method

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

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Austin, TX, United States of America

Sunil Gupta