Advanced Micro Devices Corporation

Lattice Semiconductor Corporation

Vantis Corporation

Other

Niimblecat, Inc.

Nimblecat, Inc.

Sunil D Mehta

Xiao-yu Li

Stewart G Logie

Radu M Barsan

Steven J Fong

Robert H Tu

Chun Jiang

Khanh Q Tran

Jonathan Lin

William George En

Emi Ishida

Christopher O Schmidt

Minh Van Ngo

Fabiano Fontana

Kerry A Ilgenstein

Andre N Stolmeijer

David Francis Meyer

Poonam Murgai

Fei Wang

Qi Xiang

Yowjuang William Liu

Hyeon-Seag Kim

Amit P Marathe

David Keating Foote

Darin A Chan

Jack Zezhong Peng

Brad Sharpe-Geisler

Ting Yiu Tsui

Che-Hoo Ng

Raymond T Lee

Larry R Metzger

Van Hung Pham

Chih-Chuan Lin

Nicholas R Maccrae

Xiao Yu Li

David O Seaver

Guoxin Li

A social-mobile-local (SML) system and environment includes user mobile devices, a distributed communications network over which the devices communicate, a means of sensing proximity between pairs of mobile devices, and one or more SML databases and programs resident on the user mobile devices, on remote computers, or both. Challenges addressed include prevention of 'alert flooding,' privacy protection, credential verification, entering detailed data on mobile devices, power-saving, and improved quality in both the choice and the content of notifications. Solutions include the aggregation of online information about a user to create an aggregate profile, enabling the user to create multiple personas by selecting what information from the profile or from other sources to reveal to other users under which circumstances, enabling the user to broadcast 'wants' and preview what is available in the vicinity, linguistic analysis detecting nuanced correspondences between terms entered for wants and filtering out purely incidental word-matches, and adaptive algorithms to make the best use of battery power and other resources in dynamic surroundings.

Social-mobile-local (SML) networking with intelligent semantic processing

The most common automated search methods produce less-than-ideal results when searching online resumes, profiles, and the like ('biographies') for the identities of people with a searcher-selected qualification ('candidates'). Keywords, their proximities, and their repetitions are less informative in biographies than in other informational documents. Similarly, chains of social connection (&#x201c;referral paths&#x201d;) do not always reveal the likelihood or ease of a searcher's introduction to a candidate. In both cases, the display order of results may be unrelated to any estimate of merit. To answer the question &#x201c;Whom do I need and how do I reach them?&#x201d; a classifier system uses heuristics or algorithms adapted to match the reactions of human experts on the selected qualifications. Terms in biographies, regardless of structure, are standardized and disambiguated for accurate comparisons, meaningful context is preserved, and biographies and referral paths are scored based on expected usefulness to the searcher.

Identifying and ranking networked biographies and referral paths corresponding to selected qualifications

In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low voltage transistor regions, and a third trench between the first and second trenches and between and adjacent to a high voltage transistor region and a low voltage transistor region. A thicker silicon dioxide layer lines the first trench and a first portion of the third trench adjacent to a high voltage transistor region. A thinner silicon dioxide layer lines the second trench and a second portion of the third trench adjacent to a low voltage transistor region. A silicon nitride layer is present on the thinner silicon dioxide layer and lines the second trench and the second portion of the third trench but is not present on the thicker silicon dioxide layer and does not line the first trench and the first portion of the third trench.

Shallow trench isolation (STI) with trench liner of increased thickness

A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness. A silicon nitride layer is deposited on the silicon dioxide layer in the first and second trenches. The silicon nitride layer is then etched from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench. The exposed silicon dioxide layer in the first trench is oxidized to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench. The first and second trenches are then filled with a dielectric material.

A high voltage transistor exhibiting an improved breakdown voltage and related methods are provided. For example, a method of manufacturing an integrated circuit includes etching a poly silicon layer to provide a gate stacked above a floating gate of a flash memory cell. A source and a drain of the flash memory cell are implanted in a substrate. The poly silicon layer is etched to provide a gate of a high voltage transistor. Lightly doped drain (LDD) implants are provided in source/drain regions of the high voltage transistor in the substrate. An annealing operation is performed on the integrated circuit, wherein the annealing causes each of the LDD implants to form a graded junction in relation to a channel in the substrate between the LDD regions, and further causes sidewalls to oxidize on the gates of the flash memory cell and on the gate of the high voltage transistor.

Formation of high voltage transistor with high breakdown voltage

A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation. In another embodiment of the present invention, a magnitude of the respective threshold voltage of each of the P-channel and N-channel sense transistors is higher than a magnitude of a threshold voltage of standard process P-channel and N-channel transistors. With such a higher threshold voltage, the P-channel and N-channel sense transistors do not erroneously turn on to dissipate power during the read operation, to ensure that the memory cell is a zero-power memory cell.

Zero-power programmable memory cell

In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be electrically isolated from an input to the bent-gate input stage transistor by forming at least one bent-gate grounded-gate transistor between the bent-gate output stage transistor and the input to the bent-gate input stage transistor.

Circuit layout for improved performance while preserving or improving density

In one embodiment, an EEPROM device having voltage limiting charge pumping circuitry includes charge-pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer.

EEPROM device with voltage-limiting charge pump circuit

A process for fabricating a semiconductor device having electrically isolated low voltage and high voltage substrate regions includes low voltage and high voltage trench isolation structures in which a deep portion of the high voltage isolation trench provides electrical isolation in the high voltage regions. The high voltage isolation trench structures include a shallow portion that can be simultaneously formed with the low voltage trench isolation structures. The deep portion of the high voltage isolation trench has a bottom surface and shares a continuous wall surface with the shallow portion that extends from the bottom surface to the principal surface of the substrate. A process for fabricating the device includes the formation of sidewall spacers to define a minimum isolation width between adjacent high voltage nodes.

Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions

An EEPROM device exhibiting high saturation current and low signal propagation delay and a process for fabricating the device that includes the formation of refractory metal silicide regions in the source and the drain regions and the gate electrode of an MOS transistor within an EEPROM memory cell. A floating-gate protect layer is formed over the floating-gate electrode and a relatively thick cap oxide layer is formed to overlie the floating-gate protect layer and the source and drain regions and gate electrode of the MOS transistor. A doped oxide layer is formed to overlie the cap oxide layer. The cap oxide layer is formed to a thickness sufficient to create strain in the channel region of the MOS transistor, while not having a thickness that could cause poor data retention in the EEPROM memory cell.

High-performance non-volatile memory device and fabrication process

An EEPROM device having voltage limiting charge pumping circuitry includes charge pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer. A process for fabricating the device is also provided.

Voltage limited EEPROM device and process for fabricating the device

A semiconductor device having an EEPROM memory cell includes a substrate having a principal surface and an isolation region having an inner edge surface bounding the tunnel region at the principal surface. The isolation region forms a perimeter of the tunnel region. A capacitor plate overlies the tunnel region and substantially the entire perimeter of the tunnel region. A tunnel dielectric layer overlies the tunnel region and separates the capacitor plate from the tunnel dielectric layer. The edges of the capacitor plate are displaced away from the tunnel dielectric layer to avoid a loss of tunneling current as a result of edge degradation with repeated programming and erasing of the EEPROM memory device. A process for fabrication of the device is also provided.

EEPROM device having an isolation-bounded tunnel capacitor and fabrication process

A device having electrically isolated low voltage and high voltage substrate regions includes low voltage and high voltage trench isolation structures in which a deep portion of the high voltage isolation trench provides electrical isolation in the high voltage regions. The high voltage isolation trench structures include a shallow portion that is simultaneously formed with the low voltage trench isolation structures. The deep portion of the high voltage isolation trench has a bottom surface and shares a continuous wall surface with the shallow portion that extends from the bottom surface to the principal surface of the substrate. A process for fabricating the device includes the use of a single resist pattern to simultaneously form the low voltage isolation trench structures and the shallow portion of the high voltage isolation structures.

Device having electrically isolated low voltage and high voltage regions and process for fabricating the device

A zero power memory cell includes first and second NMOS transistors and a PMOS transistor, wherein the first NMOS transistor and first PMOS transistor each include a three-implant channel region, and wherein the second NMOS transistor further includes a two-implant channel region.

Zero power memory cell with reduced threshold voltage

Growing community of inventors

San Jose, CA, United States of America

Sunil D Mehta