Texas Instruments Corporation

Sunil Chomal

Jawaharlal Tangudu

Sarma Sundareswara Gunturi

Sreenath Narayanan Potty

Karthik Ramasubramanian

Jasbir Singh Nayyar

Hemanth Mullur

Sthanunathan Ramakrishnan

Nagarajan Viswanathan

Sashidharan Venkatraman

The disclosure provides a heart rate monitor (HRM) circuit. The HRM circuit includes an analog front end (AFE). The AFE receives a Photoplethysmographic (PPG) signal, and generates a fine PPG signal. A motion cancellation circuit is coupled to the AFE, and receives the fine PPG signal and an accelerometer signal. The motion cancellation circuit subtracts the accelerometer signal from the fine PPG signal to generate a coarse heart rate. A peak detector is coupled to the motion cancellation circuit and the AFE, and generates an instantaneous heart rate. A filter is coupled to the peak detector, and generates an estimated heart rate from the instantaneous heart rate, the estimated heart rate is provided as a feedback to the peak detector.

Accuracy of heart rate estimation from photoplethysmographic (PPG) signals

A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.

Memory optimized GNSS correlator

An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit () operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit () operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

Circuits, devices, and processes for improved positioning satellite reception and other spread spectrum reception

A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC) signal and an image of the signal tone in the discrete frequency domain representation of the IADC signal and determines a correlation between the signal tone and the image of the signal tone, a power of the signal tone and a power of the image of the signal tone. The system can also include a frequency domain estimator that determines an instantaneous frequency domain mismatch profile estimate based on the correlation between the signal tone and the image of the signal tone. The system can further include an averaging filter that averages the instantaneous frequency domain mismatch profile estimate over time to provide a frequency domain mismatch profile estimate.

Mismatch profile

An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit () operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit () operable to coherently integrate the correlation results over plural sample windows (PreD, PreD) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD, PreD) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

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Bengaluru, India

Sunil Chomal