Apple Inc.

Sunil Bhosekar

Sanjeev K Maheshwari

Lizhi Zhong

Wenbo Liu

Wing Liu

Vishal Varma

Gary A Rogan

Jaeduk Han

Ming-Shuan Chen

Jose A Tierno

William D Schwarz

Erick Omar Torres

Khaled M Alashmouny

Suresh Balasubramanian

Bruce Andrew Doyle

Chad O Lackey

Sanjeev S Gokhale

Sharath R Srinivasan

An encoding/decoding scheme for pulse amplitude modulation (PAM) communications systems is disclosed. In one embodiment, a transmitter unit includes an encoder circuit and a transmit circuit. The encoder circuit is configured to encode an input data word having a first number of bits into a output data word having a second number of bits. The encoder performs a comparison operation to determine if at least one pair of subsets of the second plurality of bits includes bit values that are complements of each other. The encoder is further configured to modify the second plurality of bits if none of the pairs of subsets includes bit values that are complements of each other such that the modified second plurality of bits does include at least one pair of subsets that includes values complementary to one another.

Encoding and decoding for PAM transmitter and receiver

Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

Clock duty cycle correction

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Serial data receiver with sampling clock skew compensation

Growing community of inventors

Austin, TX, United States of America

Sunil Bhosekar