Samsung Electronics Co., Ltd.

Sungwook Moon

Seungki Nam

Taeyoon Kim

Shaofeng Ding

Jeonghoon Ahn

Yunki Choi

Jungil Son

Chanmin Jo

Yoonjae Hwang

A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

Semiconductor chip and semiconductor package including same

A semiconductor device includes pads of a first group and a plurality of first peripheral pads, which are adjacent to each other and spaced apart by a first horizontal gap in a first direction, and pads of a first group and a plurality of first peripheral pads, which are connected to each other and spaced apart by a first vertical gap, greater than the first horizontal gap, in a second direction. A plurality of first wiring patterns include first horizontal extension portions extending at an angle exceeding about 45 degrees with respect to the first direction within the first horizontal gap.

Semiconductor device

Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.

Method implemented on computer system executing instructions for semiconductor design simulation

A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.

Growing community of inventors

Yongin-si, South Korea

Sungwook Moon