Samsung Electronics Co., Ltd.

Yonsei University

Sungwoo Chung

Youngseo Lee

Hyeongkon Bae

Myungjae Chung

A memory system includes a memory module and a memory controller. The memory module stores a code word group including first and second data words and a flag. The memory controller includes an error correction code (ECC) engine including a data-width aware (DWA) encoder that generates the code word group by using the first and second data words, and performs an error detection and error correction operation in one of first to third modes based on a size of each of the first and second data words, and a DWA decoder that receives the code word group, performs an error detection and error correction operation in one of the first to third modes according to a type of the code word group determined based on the flag, and extracts the first data word and the second data word from the code word group.

Memory system including data-width aware encoder and data-width aware decoder and operating method thereof

A memory controller that controls a memory module including a plurality of memory chips, the memory controller including an error correction circuit including an encoding circuit and a processor to control the error correction circuit. The encoding circuit, in a write operation, divides a user data set into data units, generates data flags indicating types of the data units, generates data parities based on the data units, generates flag parities based on the data flags, generates an encoded user data set by using at least one null data unit in which all or half of included data bits are zero, as a data duplication space for duplicating a valid data unit, generates a codeword set by interleaving the encoded user data set, the data parities, the data flags, the flag parities and a null bit bit-wisely, and transmits the codeword set to the memory module.

Memory controllers and memory systems including the same

An integrated circuit includes; a core configured to process an instruction in accordance with a voltage-frequency level, an instruction complexity calculation circuit configured to calculate an instruction complexity for at least one instruction to-be-processed after a reference time in relation to heating information related to the core acquired before the reference time, wherein the instruction complexity calculation circuit is further configured to generate a control signal corresponding to the instruction complexity, and a dynamic voltage and frequency scaling (DVFS) controller configured to adjust the voltage-frequency level after the reference time in response to the control signal.

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Seoul, South Korea

Sungwoo Chung