Pitney Bowes Inc.

Sungwon R Moh

Arno Muller

Young W Lee

Donald T Dolan

David W Beckstrom

Edilberto I Salazar

Richard P Schoonmaker

Roger J Ratzenberger, Jr

Mark A Scribe

Yakup J Igval

Frank D Ramirez

Joan T Doutney

Peter A Pagliaro

Scott T Potter

Christina S Park

James R West

David W Hubbard

Steven J Pauly

Brad L Davies

Robert G Arsenault

William F Bailey

Eswaran C Nambudiri

Edward J Twarog

James R Ralph

David N Long

Thomas F Barraza

A cryptographic device that will actively clear its memory even in the absence of external power when a security breach is detected is provided. The memory cell clusters of the cryptographic device are provided with an internal power source that provides sufficient energy for the memory cell clusters to perform a clearing operation. If the external power source for the memory is removed and a physical security breach is detected, the power from the internal power source will allow the memory cells to actively clear their contents, thereby rendering any attempt to obtain the contents of the memory cells fruitless.

Cryptographic device having active clearing of memory regardless of state of external power

Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port.

System and method for data recovery in a disabled integrated circuit

A postage metering system includes a base and a user interface mounted to the base. The user interface includes a micro controller, an internal socket for receiving an integrated circuit chip and a smart card reader interface connector for interfacing with an external smart card. The micro controller is configurable to address either the internal socket or the smart card reader interface connector to access postage metering functionality.

Postage metering system having multiple postage meter configuration capability

A postage printing system includes a printer and a postage meter. The postage meter includes a controller for generating print information having a plurality of print data blocks necessary to print a postal indicia. The printer is located remotely from the postage meter and includes a controller and a printer for printing the postal indicia. The printer controller is in operative communication with the postage meter controller for receiving the plurality of print data blocks. The postage meter controller encrypts the plurality of print data blocks into a plurality of encrypted print data blocks, respectively, using a cypher block chaining encryption algorithm prior to transmitting the plurality of encrypted print data blocks to the printer controller where they are decrypted by the printer controller. Check numbers for each print data block and validation of the check numbers may be employed at the printer controller. Also, the printer controller may compare the validation rates of print data blocks containing significant data and those containing insignificant data for evidence of tampering.

Postage printing system including prevention of tampering with print

A mail handling system includes a printhead for printing a postage indicium on a mailpiece; a transport mechanism that moves the mailpiece past the printhead during printing of the postage indicium; a postage meter including means for accounting for a value of postage associated with the postage indicium; an image generator in operative communication with the postage meter, the image generator producing a synchronous image data stream for use by the printhead in printing the postage indicium; a buffer which receives and stores the synchronous image data stream from the image generator; apparatus for switching the image generator between an ON status whereby the image generator produces the synchronous image data stream and an OFF status whereby the image generator does not produce the synchronous image data stream based upon the occurrence of a predetermined condition; structure for transferring the stored synchronous image data stream to the printhead in an asynchronous manner; and wherein the switching apparatus regulates within a predetermined range an amount of the synchronous image data stream stored in the buffer by switching the image generator between the ON status and the OFF status thereby effectively permitting the printhead to use the synchronous image data stream in an asynchronous manner.

Apparatus and method for ensuring good print quality in a mail handling

An electronic postage meter control system having a printer for printing mixed graphic and alphanumeric information. The control system includes a programmable microprocessor in bus communication with the printer for controlling the printer and with a plurality of memory units for accounting for postage printed by the printer. The memory units include at least a first memory unit having a write access time shorter than the write access time of a second one of said memory unit, a program memory in bus communication with the programmable microprocessor having an operating program stored therein. The programmable microprocessor is able to access the operating program, an integrated circuit, the program memory, and said first and second units. The integrated circuit has an address decoding module for generating one of a plurality control signals in a unique combination in response to a respective request by the programmable microprocessor. Respective ones of the control signals are the memory write enable signals for write enabling the first or second units where write enable signals are directed to the respective memory unit. The control system further maintains the respective write enable control signals active for at least the write access time of the first memory unit in response to generation of a respective one of the write enable control signals by the address decoder. The control system further maintains the respective write enable control signal active for an additional second period such that sum period of the first period of time in combination with the second period of time is at generally equal to the write access time required by the second memory unit.

Address decoder with memory wait state circuit

A printing apparatus is disclosed which has various operating components, and which includes a single sensing means for sensing certain operational characteristics of the operating components to monitor the operational status thereof for the purpose of either providing an operator perceptible indication that a certain operational characteristic of one of the operating components is not in a condition for normal operation of the printing apparatus. The single sensing means includes a photo detecting means mounted on the inside surface of the cover of a housing for the operating characteristics of the printing apparatus, and an actuating means mounted on an ink cartridge which is mounted on and movable with a moving print head, such that the sensing means can provided an ink dication of whether the cover is open or closed, whether the ink cartridge is present or absent, whether the print head is in a proper position for commencing a normal cycle of operation, and in one variation of an alternate embodiment of the invention, whether there is sufficient ink in the ink cartridge for normal operation of the printing apparatus, and in another variation thereof, how much ink is in the ink cartridge at all times between full and insufficient for normal operation of the printing apparatus.

Multi function sensing device for printing apparatus

A method for controlling energizing of an ink jet printhead includes the steps of generating encoder pulses to a motor to activate the motor to move the printhead at a desired speed over a recording medium; generating and sending fire pulses at a fire pulse frequency from an ASIC to an ink jet printhead driver chip to selectively energize ink jet printhead nozzles to eject drops of ink onto the recording medium based on a predetermine relationship between an expected encoder pulse frequency and the fire pulse frequency; compensating for variations in the speed of the ink jet printhead movement caused by variations in the encoder pulse frequency by using the ASIC for continuously comparing the encoder pulse frequency to the fire pulse frequency and for adjusting the fire pulse frequency based upon the variations to the encoder pulse frequency to maintain the predetermined relationship thereby synchronizing the ink jet printhead movement with the energizing of the printhead nozzles.

Method and structure for controlling the energizing of an ink jet

The memory access limiting circuit detects when two or more of memory units associated with a microprocessor control system have been accessed enabled concurrently representing an error condition. The memory access limiting circuit is part of an integrated circuit. The integrated circuit also includes an address decoding for receiving the unique address signal and causing a write enable signal to be generated for the memory units and one of a plurality chip select signals to be generated for a respective one of the memory units. The monitoring circuit monitors the pin levels of the integrated circuit assigned for enabling the respective memory unit. The monitoring circuit generates a first output signal when a respective one of the memory unit chip select signals has been enabled and a second output signal when a plurality of chip select signals have been enabled. The second output signal is directed to the microprocessor for corrective action.

Multi-memory access limiting circuit for a multi-memory device

The memory security circuit detects when a memory unit has been accessed independently of an address instruction of a programmable microprocessor. The microprocessor is programmed to provide a unique address signal for write enabling a discrete memory unit. The memory unit has a write enable pin and chip select pin which when enabled in combination permits writing into the memory unit. The address decoder receives the unique address instruction and causes a write enable signal and a chip select signal to be generated for that memory unit. The write enable signal and chip select signal are to be received, respectively, by the write enable pin and the chip select pin of the memory unit. The memory security circuit monitors the write enable pin and the chip select pin of the memory unit and generates a first output signal when the memory unit has been properly addressed. A second output signal is generated when the memory unit has not been addressed by the address decoder and the write enable and the chip select signals are present at the memory unit.

Memory monitoring circuit for detecting unauthorized memory access

The printer control module is programmed to output control signals to the printer driver characterized by the data written in the control registers. The control system for a printing apparatus includes a printer unit responsive to a printer driver unit. The printer driver unit is responsive to the control system. The control system has a programmable printer control module in communication with the printer driver unit and a programmable microcomputer in bus communication with the printer control module. The microcomputer has a non-volatile memory unit for storing the data. The printer driver unit is responsive to control signals from the printer control module for driving the printer unit. The printer control module includes a buffer for holding printer data and the registers of the control module, including a control register, a shift register and a strobe width register. A strobe signal module generates a strobe signal for the printer driver unit having one of a plurality of strobe widths selected in response to the data written in the strobe width register. The control module also selectively causes one of a plurality of clock signals for the printer driver unit in response to data written in the control register. A shift module causes printer data to be delivered to the printer driver unit in one of a plurality of frame sizes in response to data written in the shift register. The programmable microcomputer is programmed to writing data into the control registers.

Control system for an electronic postage meter having a programmable

A micro control system includes a programmable microcontroller which is in bus communication with memory units and a operating power supply for providing operating power to said microcontroller. A communication module is part of the micro control system and is in communication with the data bus of the micro control system for receiving and transmitting data messages to an external device, and for encoding said transmitted data messages to conform to a serial communication protocol and decoding said received data messages. The microcontroller is programmed to generated a first control signal or a second control signal. An input-output interface is included as part of the micro control system and includes a number of switching units responsive to the first control signal of the microcontroller to place the respective switching units in a first mode of operation for providing communication between said communication module and a connector. The switching units also respond to said second control signal from the microcontroller to place said switching units in a second mode of operation for providing communication between said data bus of the micro control system and said connector to which connector the external device is attached.

Digital communication I/O port

The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers. A demultiplexer includes a plurality of inputs and a plurality of outputs, a respective output of the demultiplexer being in communication with the input of a respective one of the AND gates for selectively enabling a respective one of the AND gate in response to the state of the control signals.

Data encryption control system

An apparatus for producing an image in a mail handling machine includes a printing device and a non-volatile memory having fixed and variable image data elements stored therein, a first portion of the fixed image data elements being stored in a compressed manner and a second portion of the fixed image data elements being stored in a bit map form. The apparatus further includes a first control device for identifying at least one of the variable image data elements stored in the non-volatile memory and associated with the image and a second control device for receiving from the first control device data corresponding to the at least one of the variable image data elements associated with the image and for downloading from the non-volatile memory and combining fixed image data elements associated with the image with the at least one of the variable data elements associated with the image and for utilizing the combined fixed and variable data elements associated with the image to cause the printing mechanism to print the image.

Growing community of inventors

Wilton, CT, United States of America

Sungwon R Moh