Skhynix Inc.

Sungmook Lim

In Gon Yang

Jae Hyeon Shin

Hyung Jin Choi

Tae Ho Kim

Gil Bok Choi

Dae Hwan Yun

Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Semiconductor memory device with high electron mobility channels and method of manufacturing the same

A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.

Page buffer, memory device including the page buffer and operating method thereof

A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Memory device and operating method of the memory device

A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.

Memory device and operating method thereof

The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Memory device and method of operating the memory device

There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.

Growing community of inventors

Icheon-si, South Korea

Sungmook Lim