Qualcomm Incorporated

Sungmin Ock

Xuhao Huang

Wenjing Yin

Marzio Pedrali-Noy

Chenling Huang

An apparatus including: a phase lock loop (PLL), including: a phase detector and loop pass filter (PD/LF), including: a phase/frequency detector including a first input configured to receive a reference signal, and a second input configured to receive a feedback signal, and an output configured to produce an output signal based on the reference and feedback signals; a first capacitor; and a charge pump, including: a charging path configured to generate a charging current to charge the first capacitor based on the output signal; and a discharging path including a first resistor configured to discharge the first capacitor.

High gain low power phase detector and loop filter for phase lock loop (PLL)

A temperature-compensated low-pass filter includes a differential amplifier that controls a first transistor to pass a subthreshold current through the transistor to charge a capacitor with low-pass-filtered output voltage. A second transistor has a first terminal coupled to an input terminal of the low-pass filter and has a second terminal coupled to a current source conducting a bias current. The differential amplifier also controls the second transistor to conduct the bias current responsive to a difference between a complementary-to-absolute-temperature reference voltage and a voltage of the second terminal of the second transistor.

Temperature-compensated low-pass filter

A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.

Low-power temperature-insensitive current bias circuit

A voltage droop reduction circuit generally including a loop coupled to an output of a voltage regulator is provided. The loop includes a first current amplifier. The voltage droop reduction circuit may also include a first capacitor coupled between the output of the voltage regulator and an input of the first current amplifier.

Voltage droop mitigation circuit for power supply network

A switched-capacitor voltage divider is provided that functions to divide an input voltage only while a low-duty-cycle clock pulse signal is asserted. All the switches in the switched-capacitor voltage divider are idle during an off time for the low-duty-cycle clock pulse signal.

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Sungmin Ock