Samsung Electronics Co., Ltd.

Sungkweon Baek

Hakseon Kim

Suhwan Kim

Kihyun Hwang

Kwangmin Park

Donghwan Kim

Toshiro Nakanishi

Taehyun An

Seungjae Baik

Juwan Lim

Gabjin Nam

Jin Soak Kim

Yubin Kim

Eunae Chung

Taeyoung Kim

Dongchan Kim

Junhee Lim

Jae Hwa Seo

Kangoh Yun

Changhoon Jeon

Jaehwa Seo

A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a gate electrode on a semiconductor substrate, a gate insulating layer between the gate electrode and the semiconductor substrate, a first epitaxial layer disposed on the semiconductor substrate and at a side of the gate electrode, a second epitaxial layer disposed on the semiconductor substrate and at an opposite side of the gate electrode, a first contact plug in contact with a portion of the first epitaxial layer, and a second contact plug in contact with a portion of the second epitaxial layer. Top surfaces of the first and second epitaxial layers may be located at a level higher than a top surface of the gate electrode.

Semiconductor device and electronic system including the same

A transistor of a semiconductor device includes an isolation region, an active region disposed in the isolation region, a gate extending in a second direction on the active region, and source and drain regions respectively extending in a first direction perpendicular to the second direction in the active region on first and second sides of the gate. The source and drain regions include low-concentration source and drain doping regions including first and second low-concentration source and drain doping regions The source and drain regions further include high-concentration source and drain doping regions respectively disposed in the low-concentration source and drain doping regions and having higher doping concentrations than the low-concentration source and drain doping regions. A first length in the second direction of the first low-concentration source and drain doping regions is greater than a second length in the second direction of the second low-concentration source and drain doping regions.

A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

Semiconductor device having high voltage transistors

A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Static random access memory (SRAM) cells including vertical channel transistors and methods of forming the same

Static random access memory (SRAM) cells including vertical channel transistors

A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

Nonvolatile memory device and method of forming the same

A method of forming a semiconductor device includes forming a trench on a semiconductor substrate to define an active region, forming a radical oxide layer on a sidewall and a bottom surface of the trench, and forming a nitride layer on the radical oxide layer. The conduction band offset of the radical oxide layer is greater than the conduction band offset of a thermal oxide layer having the same thickness as the radical oxide layer.

Semiconductor device and method of forming the same

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Hwaseong-si, South Korea

Sungkweon Baek