Postech Academy-industry Foundation

Center for Advanced Soft Electronics

Sungjune Jung

Jimin Kwon

Kilwon Cho

Jae Joon Kim

Geunyeol Bae

Sanghoon Baek

Sujeong Kyung

Disclosed is a thin-film transistor-based pressure sensor including a gate electrode; a gate dielectric layer provided on the gate electrode; a semiconductor layer provided on the gate dielectric layer; and a source electrode and a drain electrode provided on the semiconductor layer, wherein each of the source and drain electrodes has an elastic body that includes: an elastic part having a protrusion; and a conductive part provided on a surface of the elastic part and having a conductive material. According to the pressure sensor and a method of manufacturing the same of the present invention, the elastic body coated with the conductive material is patterned to serve as the source electrode and the drain electrode of the pressure sensor whereby it is possible to drive an active matrix, drive the pressure sensor with low power, and manufacture the pressure sensor through a simple process.

Thin-film transistor-based pressure sensor and method of manufacturing same

Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other. Thereby, the static RAM core cell is configured such that organic transistors of the same type are arranged in the same plane and are vertically stacked, thus omitting a complicated patterning process for forming organic transistors of different types upon fabrication of a memory element, and also reducing the area occupied by the memory element to thereby increase the degree of integration of semiconductor circuits.

3D static RAM core cell having vertically stacked structure, and static RAM core cell assembly comprising same

Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other. The logic circuit of the invention is configured such that dual-gate thin-film transistors are three-dimensionally stacked, whereby the advantages of the dual-gate structure and of thin-film transistors can be exhibited together and the degree of integration can be drastically increased, and a logic gate is made in the area of a single transistor, thereby remarkably simplifying wire and circuit designs.

Logic circuitry using three dimensionally stacked dual-gate thin-film transistors

Growing community of inventors

Pohang-si, South Korea

Sungjune Jung