International Business Machines Corporation

Sun Microsystems, Inc.

Sungjun Chun

Anand Haridass

Roger Donell Weekly

Daniel Mark Dreps

Matteo Cocchini

Michael Cracraft

Wiren Dale Becker

Jinwoo Choi

Jose A Hejase

Jesus Montanez

Jason Lee Frankel

Paul Robert Walling

Mahesh Bohra

Junyan Tang

Pavel Roy Paladhi

Daniel Isaac Rodriguez

Brian Samuel Beaman

Jon Alfred Casey

Joshua C Myers

Xiaomin Shen

Kirk David Peterson

Karthick Rajamani

Charles Robert Lefurgy

Malcolm Scott Allen-Ware

Thomas Anthony Wassick

Alan J Drake

Nam Huu Pham

Steven Paul Ostrander

Victor V Zyuban

Erich Klink

Timothy Michael Skergan

Tingdong Zhou

Brian W Quinlan

Rohan U Mandrekar

Brian John Connolly

Charles L Reynolds

Jeonghee Shin

Larry D Smith

Lei Shan

Francesco Preda

Sylvain Pharand

Raymond E Anderson

Pascale Gagnon

Dierk Kaller

Brian Leslie Singletary

Ching Lung Tong

Jean Labonte

Stephanie Allard

David Edward Turnbull

Jean-Francois Bachand

Denis Blanchard

Dulce M Altabella Cabrera

Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Multicomponent module design and fabrication

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Dense via pitch interconnect to increase wiring density

Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)

A printed circuit board ('PCB') including a substrate integrated waveguide ('SIW') formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

PCB with substrate integrated waveguides using multi-band monopole antenna feeds for high speed communication

One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.

Signal via positioning in a multi-layer circuit board

A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures

One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Signal via positioning in a multi-layer circuit board using a genetic via placement solver

Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

Method for fabricating a hybrid land grid array connector

Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body

A device has a base with a mounting surface with a length and a stack, the stack having a diameter smaller than the length and fastened to the mounting surface. The stack may have a plurality of stack conductive layers in addition to a plurality of insulating layers that separate each of the plurality of stack conductive layers. The stack conductive layers may be separated in a manner that aligns them with corresponding printed circuit board conductive layers when the stack portion of the device is inserted into an aperture in a printed circuit board.

Method of making a printed circuit board copper plane repair

One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.

Growing community of inventors

Austin, TX, United States of America

Sungjun Chun