Samsung Electronics Co., Ltd.

Postech Research and Business Development Foundation

Sungju Ryu

Hyungjun Kim

Jae-Joon Kim

Wook Hwan Kim

Yonghwan Kim

Jaejoon Kim

Youngtaek Oh

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.

Neural network accelerator

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.

Sparsity-aware neural processing unit for performing constant probability index matching and processing method of the same

An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.

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Busan, South Korea

Sungju Ryu