Integrated Silicon Solution, (cayman) Inc.

Integrated Silicon Solution Incorporated

SungJin Han

A monolithic serial NOR Flash memory device includes a single semiconductor memory die with a wide input-output (IO) bus. More specifically, the monolithic serial NOR Flash memory device is configured with an input-output (IO) bus including N number of IO terminals, also referred herein as IO pins. The memory device of the present disclosure transfers commands through a subset of the N IO terminals while transferring data through all of the N IO terminals. In one example, the subset of IO terminals is N/2 IO terminals. In one example, the serial NOR Flash memory device is implemented as a serial octal (base 8) NOR flash memory device. As thus configured, the serial octal NOR flash memory device of the present disclosure transfers command though 8 IO pins, transfers address through 8 IO pins or 16 IO pins, and transfers data though 16 IO pins.

Monolithic serial NOR flash with wide input-output bus

A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output data using the double data rate mode.

SPI NOR memory with optimized read and program operation

A memory device implements a memory read training method using a dedicated read command to retrieve training data from a register for performing memory read training while the memory device remains operating in the normal operation mode. Subsequent to the memory read training, the memory device may then receive the normal read command to read data from the memory cell array or the normal write command to write data to the memory cell array. In this manner, memory read training is performed simply by issuing read commands and carrying out read operations without requiring the memory device to enter and exit special memory read training mode for performing calibration.

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San Jose, CA, United States of America

SungJin Han