Electronics and Telecommunications Research Institute

Sungjae Chang

Hokyun Ahn

Hyunwook Jung

Hae Cheon Kim

Hyung Sup Yoon

Jong-Won Lim

Dong Min Kang

Byoung-Gue Min

Sang-Heung Lee

Seong-Il Kim

Hong Gu Ji

Dong-Young Kim

Jongmin Lee

Kyu Jun Cho

Jae Won Do

Min Jeong Shin

Woojin Chang

Hyung Seok Lee

Yoo Jin Jang

Jeong Jin Kim

Provided is a compound semiconductor device. The compound semiconductor device according to embodiments of the inventive concept includes a first semiconductor layer having a fin extending in a first direction on a substrate, an upper gate electrode extending in a second direction perpendicular to the first direction on the first semiconductor layer, a second semiconductor layer disposed between a sidewall of the fin and the upper gate electrode, a dielectric layer disposed between a top surface of the fin and the upper gate electrode, and a lower gate structure connected to a bottom surface of the first semiconductor layer by passing through the substrate.

Compound semiconductor device

Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.

Semiconductor device having a drain electrode contacting an epi material inside a through-hole and method of manufacturing the same

Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.

Cascode switch circuit including level shifter

Growing community of inventors

Daejeon, South Korea

Sungjae Chang