Samsung Electronics Co., Ltd.

Sunghun Jung

Heonjong Shin

Doohyun Lee

Minchan Gwak

Yongsik Jeong

Sangwon Jee

Inchan Hwang

Sora You

Jongwoo Kim

Hakryoul Kim

Hwichan Jun

Sungyong Bang

Hyunho Park

Hakyoon Ahn

Sungmoon Lee

Yeongchang Roh

Sangmin Lee

Mooyoung Kim

Noyoung Chung

Renju Chirakarotu Nair

Myungsoo Noh

Vaisakh Punnekkattu Chirayil Sudheesh Babu

Dawoon Choi

Nikhil Sahni

Jaitirth Anthony Jacob

Aditya Jhawar

Aditi Jaiswal

Suraj Jha

An electronic device includes a sensor, a communication circuit, and a processor configured to learn a scenario based on use of the electronic device in a first temperature range, determine, using the communication circuit and/or the sensor, whether a place element of the electronic device is changed, start the scenario based on determining that the place element is changed, estimate an ambient temperature of the electronic device based on the scenario, and enter a second heating control mode at a second temperature different from a first heating control mode at a first temperature, based on the estimated ambient temperature being different from an internal temperature of the electronic device.

Electronic device and controlling method therefor

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

Integrated circuit device

A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

Semiconductor device having a source/drain contact plug with an upwardly protruding portion

Methods and systems for ascertaining factors contributing to the temperature of a device. A method includes monitoring a plurality of parameters that are contributing to a temperature of the device. The method also includes estimating a degree of contribution of internal factors to the temperature of the device based on the monitored plurality of parameters and a battery temperature of a battery of the device. The method further includes estimating a degree of contribution of external factors to the temperature of the device, based on the monitored plurality of parameters and a battery temperature of a battery of the device. A neural network can be used for estimating the temperature of the ambience of the device and the impacts of internal and external factors on temperature of the device.

Methods and systems for ascertaining factors contributing to the temperature of a device

A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

Semiconductor device

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

Active regions via contacts having various shaped segments off-set from gate via contact

A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

Semiconductor device having silicides and methods of manufacturing the same

Method of manufacturing a semiconductor device having a source/drain contact plug with a recessed portion using a mask pattern layer

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Suwon-si, South Korea

Sunghun Jung