Samsung Electronics Co., Ltd.

Sunghoi Hur

Sunil Shim

Kwang Soo Seol

Hansoo Kim

Jaehoon Jang

Su-Youn Yi

Kihyun Kim

Changhyun Lee

Jaehun Jeong

Kwangmin Park

Hanmei Choi

Chanjin Park

Toshiro Nakanishi

Wansik Hwang

Jinho Kim

Kihyun Hwang

Jungdal Choi

Juyul Lee

Byungkyu Cho

Younggoan Jang

Jang-Gn Yun

Seong Soon Cho

HuiChang Moon

Joon-Sung Lim

Hoosung Cho

Jaesun Yun

Taekyung Kim

Jintae Kang

Jaeduk Lee

Jinman Han

Jintaek Park

Jang-Hyun You

Doogon Kim

Jongin Yun

Sung-Min Hwang

Ki-Hyun Hwang

Sunyoung Kim

Kwang-Soo Seol

Dongchul Yoo

Dohyun Lee

SeungHyun Lim

Dae Sin Kim

Albert Fayrushin

Yong-lack Choi

Homin Son

Daewoong Kang

Changyun Lee

Jaeho Jeong

Ju-Yul Lee

Changsub Lee

Nambin Kim

Kim Taekyung

Sunhil Shim

Kwnag Soo Seol

A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Semiconductor device, systems and methods of manufacture

A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

Semiconductor devices and methods for forming the same

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

Three-dimensional semiconductor devices having vertical structures of different lengths

An electrode structure includes a plurality of electrodes vertically stacked on a substrate. Each of the plurality of electrodes includes an electrode portion, a pad portion and a protrusion. The electrode portion is parallel to a top surface of the substrate, extending in a first direction. The pad portion extends from the electrode portion in an inclined direction with respect to the top surface of the substrate. The protrusion protrudes from a portion of the pad portion in a direction parallel to the inclined direction. Protrusions of the plurality of electrodes are arranged in a direction diagonal to the first direction when viewed from a plan view.

Three-dimensional semiconductor device and method of manufacturing the same

In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby

Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

Semiconductor device

Growing community of inventors

Seoul, South Korea

Sunghoi Hur