Samsung Electronics Co., Ltd.

Sunghee Han

Yoosang Hwang

Kiseok Lee

Taejin Park

Keunnam Kim

Hui-Jung Kim

Sohyun Park

Bong-Soo Kim

Dongoh Kim

Wooyoung Choi

Chulkwon Park

Inkyoung Heo

Junsoo Kim

Hyeonok Jung

Euna Kim

Satoru Yamada

Hyeongsun Hong

Bongsoo Kim

Sang-Il Han

Hyosub Kim

Jinwoo Bae

Hyo-Sub Kim

Jin-Hwan Chun

Chansic Yoon

Kyupil Lee

Kyujin Kim

Sangho Lee

Taehoon Kim

Eun Ah Kim

Junwon Lee

Dongjun Lee

Myeong-Dong Lee

Junghwan Oh

Jaehwan Cho

Daehyoun Kim

Daewon Kim

Seung-Heon Lee

Chan-Sic Yoon

Daeik Kim

Jemin Park

Chan Ho Park

Seok H Lee

Huijung Kim

Junhyeok Ahn

Wonwoo Lee

Sooho Shin

Seokhan Park

Hyeon-Kyu Lee

Youn-seok Choi

Yoonjae Kim

Deoksung Hwang

Jae Hyun Yoon

Hyo-sun Min

Myeongdong Lee

Soyeong Kim

Woosong Ahn

Woonghwi Bae

Chaelin Yoon

Sunwoo Heo

Inwoo Kim

An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Method of forming an integrated circuit devices having buried word lines

An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

Integrated circuit device

The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Semiconductor devices having improved electrical characteristics and methods of fabricating the same

A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

Semiconductor and manufacturing method of the same

Integrated circuit devices having buried word lines therein

A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

Semiconductor memory devices

A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

Semiconductor devices

A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device

A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof.

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Semiconductor memory device having spacer capping pattern disposed between burried dielectic pattern and an air gap and method of fabricating same

Semiconductor device and manufacturing method of the same

A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device

A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

Semiconductor memory device

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Hwaseong-si, South Korea

Sunghee Han