Samsung Electronics Co., Ltd.

Sungcheol Park

Sanghoon Lee

Kiseok Bae

Jehyun Park

Hyungil Woo

Jieun Ahn

Sangsoon Im

Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.

Logic BIST circuit and semiconductor device including same

A semiconductor integrated circuit to receive a test scan input, a test clock, and a test mode signal and output a secure scan output signal, the integrated circuit including: a secure key circuit to generate delay input signals, which are differently delayed from the test scan input, and to generate an input key signal by capturing the delay input signals in response to the test clock; a key comparator to generate a verification result indicating whether an input key of the input key signal is identical with a preset reference key; a chip to generate a scan output signal based on the test scan input; a scan output remapper to obfuscate the scan output signal according to the verification result and to output the obfuscated scan output signal as the secure scan output signal; and a secure scan controller to control the secure key circuit, key comparator, chip, and remapper.

Semiconductor integrated circuit, a method for testing the semiconductor integrated circuit, and a semiconductor system

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

Integrated circuit and operating method thereof

Provided herein are an apparatus and a method of performing image noise filtering with respect to an image obtained from an image sensor, the method including: applying a noise deviation with respect to a temporal difference between a previous pixel value and a current pixel value when obtaining a temporal weight value to be used in temporal filtering. The noise deviation is obtained according to an intensity level of the current pixel value. Temporal filtering and spatial filtering may be performed, and blending filtering may be selectively performed by blending an output value of the temporal filtering and an output value of the spatial filtering.

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Seoul, South Korea

Sungcheol Park