Samsung Electronics Co., Ltd.

Woory Industrial Company Ltd.

University-Industry Cooperation Group of Kyung Hee University

Snu Rdb Foundation

Sung-young Lee

Eun-jung Yun

Sung-Min Kim

Dong-Gun Park

Chang-Woo Oh

Min-sang Kim

Jeong-Dong Choe

Hye-Jin Cho

Dong-Suk Shin

Dong-Won Kim

Sung-min Kim

Shin-Ae Lee

Chang-Sub Lee

In-Hyuk Choi

Sung-Dae Suk

Kyoung-hwan Yeo

Su-hyeon Kim

Hong-Moon Chun

Min-Su Jung

Tae-Jin Ahn

Yong-Seok Lee

Sang-Hyeon Kim

SoYeon Ahn

Taesung Park

Jin-A Mock

Tae-Hwan Kang

Ki-Deuk Kim

Jung-Woong Hyun

Hyun-Jun Kwon

Joon-mo Kwon

Asad Masood Khattak

Sung-ho Won

Seung-yeoun Lee

Bora Yeon

Young-ho Park

Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

Gate-all-around integrated circuit devices

Provided is a data processing method for clinical decision support system. The data processing method provides an algorithm capable of performing parsing based on an Ontology technique and automatically updating rule database in order to reduce time and labor overloads accompanied by update of the rule database. According to an aspect, the data processing method includes inferring input data having a natural language format based on an Ontology technique to recognize at least one input rule included in the input data; inferring storage data having a natural language format and stored in rule database based on the Ontology technique to recognize at least one storage rule associated with the input rule from the storage data; comparing the input rule to the storage rule using a Self Evolutionary Rule-base algorithm; and updating the storage data stored in the rule database to the input data according to the result of the comparison.

Data processing method and apparatus for clinical decision support system

A method of recovering a nucleic acid sequence using a probe map includes: aligning a probe onto a target sequence based on a result in which the probe is hybridized to the target sequence; determining a representative value representing each aligned position of the probe; and recovering a base sequence of the target sequence by using a probe map to which the determined representative values and base sequence information of the probe are mapped.

Method and apparatus for recovering gene sequence using probe map

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region.

Methods of forming semiconductor-on-insulating (SOI) field effect transistors with body contacts

In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.

Semiconductor device having a multi-channel type MOS transistor

A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

Semiconductor device and method of manufacturing same

A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Nonvolatile memory devices having stacked structures and methods of fabricating the same

Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided.

Methods of fabricating electromechanical non-volatile memory devices

A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

Methods of fabricating vertical twin-channel transistors

Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

Metal oxide semiconductor field effect transistors (MOSFETs) including recessed channel regions and methods of fabricating the same

In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.

Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures

A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same

Growing community of inventors

Gyeonggi-do, South Korea

Sung-young Lee