Lg Electronics Inc.

Hynix Semiconductor Inc.

Yonsei University

Sung Yoon Cho

Byoung Hoon Kim

Dong Ku Kim

Hyuk Jin Chae

Han Byul Seo

Kaibin Huang

Soon Suk Roh

Ki Jun Kim

Jung Park

Jae Heon Kim

Choi Dong Kim

Woo Young Jung

Jin Young Jang

Ik Soo Choi

Pil Keun Song

Provided is a method and a device for precoding in a wireless communication system. The method for precoding comprises the following steps: generating a first precoding matrix, W, for deciding the transmission power of one transmission antenna from a plurality of transmission antennas as the maximum power per antenna; generating a zero forcing (ZF) precoding matrix, T, which does not influence the transmission antenna having the power which is decided as the maximum power per antenna, based on the (i&#x2212;1)precoding matrix W(i=2, 3, . . . ); determining &#x3b1;, a constant which has the transmission power of one transmission antenna from the rest of the transmission antennas, which do not have the transmission power as the maximum power per antenna, based on the T; and generating the iprecoding matrix Wbased on the Tand the &#x3b1;.

Method and device for precoding in wireless communication system

A feedback method for interference alignment in wireless network having K transmitters and K receivers, the method including: transmitting, by a transmitter n&#x2212;1, a precoding vector of the transmitter n&#x2212;1 (n being an integer between 2 and K&#x2212;1) to a receiver n+1; calculating, by the receiver n+1, a precoding vector of a transmitter n using the precoding vector of the transmitter n&#x2212;1; and transmitting, by the receiver n+1, the precoding vector of the transmitter n to the transmitter n.

Feedback method for interference alignment in wireless network

A method for interference alignment in wireless network having 3 transmitters and 3 receivers which are equipped with M antennas is provided. The method comprising: transmitting, performed by each of the 3 transmitters, a pilot signal known to the 3 receivers; estimating, performed by each of the 3 receivers, each channel from transmitter; transmitting, performed by each of the 3 receivers, feedback information to target transmitter; and determining, performed by transmitter 2 and transmitter 3, a precoding vector; wherein a degree of freedom (DoF) of a transmitter 1 is (M/2&#x2212;&#x3b1;), a DoF of the transmitter 2 or the transmitter 3 is M/2.

Method for interference alignment in wireless network

A power control method for interference alignment in wireless network having K transmitters and K receivers is provided. The method includes: receiving, performed by receiver n (n is an integer, 1&#x2266;n&#x2266;K&#x2212;1), a power indication signal of transmitter n+1 from the transmitter n+1; determining, performed by the receiver n, power of transmitter n; and transmitting, performed by the receiver n, a power indication signal of transmitter n to the transmitter n, wherein the power of transmitter n is determined based on a residual interference of the receiver n, and the power indication signal of transmitter n indicates a minimum transmission power or a maximum transmission power of transmitter n.

Power control method for interference alignment in wireless network

A method for fabricating a flash memory device includes forming a control gate having a hollow donut shape over an insulation layer formed over a substrate. The method also includes forming an inter-poly dielectric of a spacer shape on an inner wall of the control gate, filling a conductive layer for a floating gate between the spacer shaped inter-poly dielectrics, and forming an interlayer insulation layer over a resulting product formed with the conductive layer for a floating gate. The method further includes removing a center portion of the conductive layer for a floating gate to form an opening, forming a tunnel insulation layer on an inner face of the opening, and filling with a semiconductor layer the opening formed with the tunnel insulation layer to form an active region.

Method for fabricating flash memory device having vertical floating gate

In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern.

Method for forming fine pattern by spacer patterning technology

A method of forming a micro pattern in a semiconductor device, wherein a first polysilicon film, a buffer oxide film, a second polysilicon film, an anti-polishing film, and a first oxide film are sequentially laminated on a semiconductor substrate having a to-be-etched layer. The first oxide film, the anti-polishing film and the second polysilicon film are patterned. After nitride film spacers are formed on the patterned lateral portions, a second oxide film is formed on the entire structure. A Chemical Mechanical Polishing (CMP) process is performed using the anti-polishing film as a stopper. Thereafter, after the nitride film spacers are removed, the second oxide film and the second polysilicon film are removed using a difference in etch selective ratio between the oxide film and the polysilicon film. A hard mask for forming a micro pattern having a structure in which the first polysilicon film and the buffer oxide film are laminated is formed. The to-be-etched layer is etched using the hard mask as an etch barrier.

Method of forming micro pattern in semiconductor device

A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined. The method comprises the steps of: sequentially forming an insulating layer and an Anti-Reflective Coating layer on a substrate, the substrate including conductive regions; forming a photoresist pattern opening in the Anti-Reflective Coating layer over the conductive regions; removing the Anti-Reflective Coating layer in accordance with a first dry etch process using a mixed gas of SO and He and employing the photoresist pattern as an etch mask and at the same time, attaching polymers resulting from the dry etch process to the side of remaining Anti-Reflective Coating layer, thereby forming a polymer sidewall; removing the insulating layer in accordance with a second dry etch process employing the photoresist pattern and the polymer sidewall as an etch mask, thereby forming a contact hole; and removing the photoresist pattern, the remaining Anti-Reflective Coating layer and the polymer sidewall.

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Seoul, South Korea

Sung Yoon Cho