Skhynix Inc.

Markany Inc.

Sung Wook Jung

Ji Hui Baek

Dong Hun Lee

Go Hyun Lee

Hye Eun Heo

Tae Hwa Lee

Jang Hee Jung

Jin Ho Kim

Jung Seok Oh

Yu Jin Park

Dong Kee Lee

Jong Uk Choi

Hyun Seung Yoo

Go-Hyun Lee

Jiyeon Kim

Dongha Shin

Muhammad Ali Malik

Kyung Bo Kim

A three-dimensional (3D) semiconductor device includes a plurality of stack structures, a plurality of channel plugs, a slit structure and a plurality of dummy channel plugs. The stack structures include at least two conductive layers and at least two insulation layers, each being alternately stacked. The channel plugs are vertically formed through the stack structure. The slit structure is arranged at one side of the stack structure. The plurality of dummy channel plugs is arranged in the stack structures to be adjacent to the slit structure. Each of the channel plugs includes a channel insulation layer and a channel layer. Each of the dummy channel plugs includes at least one of the channel insulation layer, the channel layer, and a material of the plurality of conductive layers.

Three-dimensional semiconductor device and method of manufacturing the same

A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.

Method for fabricating semiconductor memory device including channel posts of different shapes

A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.

Semiconductor devices

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.

Semiconductor memory device including pass transistors with variable sizes

Semiconductor memory device including at least one channel post with a first curved portion and a second curved portion having different curvatures and method for fabricating the same

A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

A semiconductor memory device includes an electrode structure including a plurality of gate conductive films stacked on a substrate and a channel array in which a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns may include a first column whose uppermost plane has a first shape and a second column whose uppermost plane has a second shape. N (N is a natural number equal to more than 1) first columns and N second columns are alternately arranged in a first direction different from the second direction.

Semiconductor memory device

A semiconductor memory device includes a cell string with a plurality of selection transistors, a plurality of dummy transistors and a plurality of memory cell transistors coupled in series therein and a pass transistor (TR) unit with a plurality of pass transistors that transmit a plurality of driving signals to the cell string. The pass TR unit includes a plurality of first pass transistors transmitting a first driving signal with a first level voltage, among the plurality of driving signals, to the plurality of selection transistors, respectively, and a plurality of second pass transistors transmitting a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, to a plurality of dummy transistors, respectively. Each of the second pass transistors has a larger channel area than each of the first pass transistors.

A semiconductor device may include first conductive patterns and first interlayer insulating layers. Each of the first conductive patterns may include a first pad pattern extending in a first direction and first line patterns extending from the first pad pattern in a second direction crossing the first direction, widths of the first line patterns increasing as a distance from the first pad pattern decreases. The first conductive patterns and the first interlayer insulating layers may be stacked on top of each other.

Semiconductor device

A nonvolatile memory device may include a plurality of memory blocks each including a drain select line, word lines and a source select line, and a pass transistor stage including a plurality of pass transistors formed in series in an active region and suitable for transferring word line voltages to a memory block selected among the memory blocks, in response to a block select signal, wherein the pass transistors each share a drain with a first adjacent pass transistor at one side while sharing a source with a second adjacent pass transistor at the other, and wherein a pair of pass transistors which share the source transfer word line driving signal form drains thereof to a pair of word lines which are included in different memory blocks among the memory blocks, through the source.

Nonvolatile memory device

Disclosed is a semiconductor device, including: a memory block including a plurality of memory strings, each of the memory strings including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, memory cells coupled to the drain select transistor and the source select transistor, and dummy memory cells coupled to the drain select transistor and the memory cell; and an operation circuit configured to perform a program operation on the memory cells. The operation circuit generates operation voltages applied to the dummy memory cells so that electric charges are generated by a band to band tunneling effect in the dummy memory cell adjacent to the drain select transistor during the program operation.

A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.

Growing community of inventors

Gyeonggi-do, South Korea

Sung Wook Jung