Samsung Electronics Co., Ltd.

Sung-wook Hwang

Joonsoo Park

SoonMok Ha

Yeoung-jun Cho

Tae-Young Lee

Sang-Sub Song

Joon-young Oh

Ki-Hong Jeong

Dae-Yong Kang

Byungjun Jeon

Seongho Moon

Tae-Heum Kim

Eunshoo Han

A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package. When implemented as a package housing a memory controller, DRAM semiconductor chips and non-volatile memory chips, locating the memory controller in a lower layer of the semiconductor package facilitates usage of the package substrate as a redistribution layer to provide communications between the memory controller and the DRAM and non-volatile memory chips.

Semiconductor package

A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.

Solid state drive package and data storage system including the same

The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.

Methods for forming fine patterns of semiconductor device

Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

Methods of forming fine patterns for semiconductor devices

Growing community of inventors

Seongnam-si, South Korea

Sung-wook Hwang