Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Hyundai Electronics Industries Co. Ltd.

Sung-Wook Hwang

Jong-Hyun Lee

Jae-Seok Yang

Dong-Gyun Kim

Ji-Young Jung

Dae-kwon Kang

Chul-Ho Shin

Do-Haing Lee

Jae-Il Park

In-Wook Oh

Min-Soo Kang

Kyeong-Koo Chi

Chung-woo Kim

Chang-Jin Kang

Jin-Seok Lee

Soo-doo Chae

Byeong-Ok Cho

Jeong-Hee Han

Jong-Woo Sun

Choong-Man Lee

Jae-Hee Ha

Sung-Chan Park

Sung-Hoon Chung

Yung-hee Yvette Lee

Sang-Heup Moon

Chul-ho Shin

Chan-jin Park

Jae-Sung Cho

An integrated chassis control method to improve driving stability may include mountain-road integrated chassis control allowing, when a road on which a vehicle drives is checked to be the route of a mountain road by an integrated chassis controller, electronic control suspension (ECS) damping force and all wheel drive (AWD) driving force distribution to be controlled in a different manner according to uphill and downhill roads due to a difference of elevation of the mountain road.

Integrated chassis control method to improve driving stability on mountain road and vehicle using the same

An integrated chassis control method may include stability control after avoidance performing stability steering assist control after avoiding a forward collision situation by avoidance steering assist control when the forward collision situation is verified by an integrated chassis controller.

Integrated chassis control method based on stability after avoidance and vehicle using the same

A method for emergency steering control may include system cooperation control in which secondary collision avoidance is performed after forward collision avoidance by cooperatively controlling Emergency Steering Assist System (ESA) control through intervention in control of a Lane Keeping Assist System (LKAS) against excessive steering that causes lane departure in the ESA control when emergency steering is detected by an emergency steering controller in a forward collision situation.

Method for escape steering control using system cooperation and vehicle thereof

A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout

Test pattern, test method for semiconductor device, and computer-implemented designing integrated circuit layout

A vehicle according to an exemplary embodiment of the present invention includes an electronic chassis control system configured for an electronic control suspension (ECS), a motor driven power steering system (MDPS), an electronic stability control (ESC), and an all wheel drive (AWD), and an integrated controller implementing an integrated avoidance control in which controls for each of the MDPS, the ESC, and the AWD according to an emergency avoidance control of the ECS in the forward collision situation, wherein it is possible to safely and rapidly avoid risk of forward collision, and cooperative control performance of the ECS and the AWD, the ESC and the MDPS is optimized by applying an emergency grade to the integrated avoidance control.

Integrated control method for improving forward collision avoidance performance and vehicle therefor

A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

Wiring structure and method of forming a wiring structure

In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.

Method of decomposing layout of semiconductor device and method of manufacturing semiconductor device using the same

A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

Layout decomposition methods and systems

A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

Method of decomposing layout of semiconductor device for quadruple patterning technology process and method of manufacturing semiconductor device using the same

A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

Layout design methods and layout design systems for performing the layout design methods

A substrate processing method may include forming a plasma; extracting ions from the plasma and accelerating the ions to have uniform or substantially uniform directivity using a grid system; irradiating the ions at a reflector, wherein the reflector includes a plurality of reflecting plates each having a metal plate and an insulating layer on the metal plate, wherein the reflecting plates are parallel or substantially parallel such that the insulating layers are exposed to the ions; reflecting the ions incident on the reflecting plates away from the insulating layers of the reflecting plates; colliding the ions reflected away from the insulating layers with the metal plates to convert the ions into neutral beams; and irradiating the neutral beams onto a substrate to process the substrate.

Substrate processing methods for reflectors

Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Methods of manufacturing non-volatile memory devices having insulating layers treated using neutral beam irradiation

A package-on-package (POP) package in which semiconductor packages are stacked using lead lines rather than conventional solder balls, and a fabricating method thereof are provided. According to the POP package and the fabricating method thereof of the present invention, the POP package is prevented from being short-circuited even when an underlying semiconductor package gets thicker and the POP package can sufficiently withstand deformation caused by post-fabrication warpage.

Growing community of inventors

Seoul, South Korea

Sung-Wook Hwang