Samsung Electronics Co., Ltd.

Korea University Research and Business Foundation

Sung-Woo Park

Ji-hoon Park

Ji-Hyun Park

Heung-Kyu Kwon

Su-Min Park

Min-Ok Na

Sung-Taeg Kang

Seong-Gyun Kim

Bo-Young Seo

June Moon

Jeong-Uk Han

Seung-Beom Yoon

Sang-Woo Kang

Ho-Joong Kwon

Jung-Hyun Park

Min-Ho Kim

Eun-Yong Kim

Joseph Jeon

Chang-Hoon Choi

Jee-Woong Kang

Eui-Jun Park

Yong-Deok Chang

Sung-Kyu Jung

Doo-Chan Hwang

Jin-Woo Park

Donghan Kim

Soon-Young Yoon

Min-Su Kim

Jung-Hwan Kim

In-Seok Hwang

Jin-Sung Kim

Keun-Chul Hwang

Sung-Soo Hwang

Inkyu Lee

Jun Young Heo

Chung-Gu Kang

Kwang-Jin Bae

Woo-Jae Kim

Soong-Yoon Choi

Heon-Ki Chae

So-Young Lim

Seung-won Kang

Young-Hoon Ro

Byoung-Ho Kim

Yung-Cheol Kong

Young-Nam Oh

Pa-Lan Lee

Yun-pil Yeom

Jin-hyuk Ahn

Weon-ho Park

Tai-Hyun Eum

Ji-Sun Hong

Seong-Jin Moon

Hae-Joo Jeong

Tae-Hwan Cha

Seung-Won Kang

Yui-Yoon Lee

Keun-Chul No 1209-703 Jugong 12Danji Apt Hwang

Young-Hoon No 502-1301 Jugong 5 Danji Apt Kwon

Yong-Deok 105-705 Dongsuwon Lg Village Chang

Hae-Joo 8-1005 Seongsan Siyoung Apartment Jeong

An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

Stacked semiconductor packages

A method for fabricating a semiconductor package including mounting a first semiconductor chip on a first substrate, disposing a first connector on the first substrate, placing a molding control film on the first semiconductor chip to horizontally extend over the first substrate, filling a space between the molding control film and the first substrate with a molding compound such that the molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and does not cover a top surface of the first semiconductor chip, detaching the molding control film, forming an opening through the molding compound to expose a portion of the first connector, disposing a second connector and a second semiconductor chip on opposite surfaces of a second substrate, respectively, and placing the second substrate on the first substrate such that the second connector contacts the first connector may be provided.

Method of fabricating a semiconductor package

A transmission method and apparatus are provided for use in a wireless communication system in which a cell includes a plurality of sub-cells. A Transmission Point (TP) in the wireless communication system includes a transmitter configured to transmit a signal to each of the plurality of sub-cells through a plurality of antennas; a receiver configured to receive uplink control information from a User Equipment (UE) located within at least one of the plurality of sub-cells; and a controller configured to determine a virtual matrix for each of the plurality of sub-cells, to select a precoding matrix according to the virtual matrices of the plurality of sub-cells, to determine a cooperative transmission mode or a normal transmission mode, based on the received uplink control information, and to control the transmitter to perform downlink transmission on a sub-cell basis through the virtual matrices of the sub-cells according to the determined transmission mode.

Transmission method and apparatus in a wireless communication system in which a cell includes a plurality of subcells

Apparatus for stacked semiconductor packages and methods of fabricating the same

An apparatus and method for transmitting in a multi-user multi-antenna system are provided. The apparatus includes a precoder for orthogonalizing a channel by removing a channel element of a corresponding terminal with respect to multiple terminals, for determining an effective channel of each terminal by decomposing the orthogonalized channel using Singular Value Decomposition (SVD), for determining a precoding matrix using the effective channel, and for mapping data streams of the multiple terminals to a plurality of transmit antennas using the precoding matrix, and the plurality of the transmit antennas for transmitting the data streams of the multiple terminals. Hence, it is possible to obtain an iteration algorithm performance requiring considerable computation while avoiding complexity and reducing computation.

Apparatus and method for precoding using channel orthogonalization in multi-user multi-antenna system

An apparatus and a method for selecting a transmission mode in a multi-antenna system are provided. The method includes checking a channel characteristic of a transmitting end using a signal received over at least two antennas; and determining a multi-antenna transmission mode according to the channel characteristic. Accordingly, the loss of the system capacity gain can be reduced and the capacity gain of the system can be increased.

Apparatus and method for selecting transmission mode in multi-antenna system

Systems employing a stacked semiconductor package

An apparatus and method for allocating a channel and power by a Base Station (BS) in a communication system are provided. The method includes, performing one of a first scheduling, which uses inter-cell cooperation information received from at least one neighboring BS and a data rate received from each User Equipment (UE), and a second scheduling, which uses both an average data rate for each subchannel computed by accumulating the data rates for a preset time period and the inter-cell cooperation information, selecting a UE to be allocated each subchannel in each subframe based on results of the performed scheduling, computing a power metric for each of the selected UE and a non-selected UE by using the inter-cell cooperation information, the average data rate, an amount of performance change of the selected UE, and the results of the performed scheduling; and allocating power to all UEs including the selected UE and the non-selected UE by preset subframe periods by using the computed power metric.

Apparatus and method for allocating channel and power in communication system

A package on package structure is provided. The package on package structure may include a first substrate having a first center region and a first C-shaped edge region at a first end of the first center region. In example embodiments, the first C-shaped edge region may faun a first space. The package structure may further include at least two first connection pads on an inner surface of the first C-shaped edge region and the at least two first connection pads may be arranged to face one another. In example embodiments, at least one first solder ball may be arranged in the first space and the at least one first solder ball may be connected to the at least two first connection pads.

Package on package

A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.

Semiconductor housing package, semiconductor package structure including the semiconductor housing package, and processor-based system including the semiconductor package structure

An electronic apparatus includes a display panel which displays an image; a cover unit which covers the display panel; and support system including a support member. The support member which includes a hinge unit which is rotably formed in the forward and backward directions in the rear side of the cover unit, a first support which is downwardly bent and extends from the hinge unit, and a second support which is upwardly bent and extends from the hinge unit. The configuration of the support system on the electronic apparatus permits a stable support at a variety of angles on an installation plane.

Electronic apparatus with stable support member system

A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.

Voltage supply device and nonvolatile memory device having the same

A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Non-volatile memory devices and methods of forming the same

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Gyeonggi-do, South Korea

Sung-Woo Park