Samsung Electronics Co., Ltd.

Sung-won Yun

Hyejin Yim

Sang-Wan Nam

Il Han Park

Chi-Weon Yoon

Han-jun Lee

Chiweon Yoon

Donghyuk Chae

Dong-Hyuk Chae

Kyung-Hwa Kang

Minsu Kim

Youngmin Kim

Minseok Kim

Kihwan Choi

Jung-Yun Yun

Oh-Suk Kwon

Jung-hoon Park

Su-Yong Kim

Jong-Yeol Park

Jinyub Lee

Hye-Jin Yim

A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

Nonvolatile memory device, operation method of a nonvolatile memory device, and operation method of a controller

A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

Memory device including massbit counter and method of operating the same

A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

Nonvolatile memory device

Nonvolatile memory device, storage device, and operation method of storage device

Memory device including massbit counter configured to perform off cell counting and method of operating the same

A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

Nonvolatile memory device and program method and program verification method thereof

A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.

Nonvolatile memory device and method of programming with bit line programming forcing voltage and programming inhibition voltage

A storage device includes a nonvolatile memory device and a controller configured to generate a read command according to a request of an external host device and transmit the read command to the nonvolatile memory device. The nonvolatile memory device is configured to perform a read operation in response to the read command, to output read data to the controller, and to store information of the read operation in an internal register.

Storage device including nonvolatile memory device and controller and operating method of the storage device

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

Nonvolatile memory device and method of programming the same

A method is for operating a nonvolatile memory device, the nonvolatile memory device including at least one string connected to a bit line, the at least one string including a plurality of memory cells connected in series, each of the plurality of memory cells being connected to a respective word line among a plurality of word lines and stacked in a direction perpendicular to a substrate. The method includes applying a word line voltage needed for an operation to a first word line among the word lines, applying a recovery voltage higher than a ground voltage to the first word line after the operation, and then floating the first word line.

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Suwon-si, South Korea

Sung-won Yun