Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Sung Won Jeong

Shang Hoon Seo

Seung Yeop Kook

Ha Young Ahn

Ji Hoon Kim

Sun Ho Kim

Young Gwan Ko

Jin Won Choi

Ki Taek Lee

Gi Sub Lee

Ji Hyun Lee

Dong Gyu Lee

Da Hee Kim

Hueng Jae Oh

Han Bit Kim

Myung Sam Kang

Dae Young Lee

Doo Hwan Lee

Jin Ho Kim

Tae Hong Min

Dae Hyun Park

Eun Jung Jo

Mi Ja Han

Christian Romero

Jong-Deok Choi

Hyun Seok Cha

Jong Hyun Yoon

Ju Hyeon Kim

Heung Jae Oh

Dae Kyu Ahn

A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer, and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. At least a portion of a first wall of a first trench of the first insulating layer and at least a portion of a second wall of a second trench of the second insulating layer overlap each other vertically. At least a portion of the second wall of the second trench and at least a portion of a third wall of a third trench of the third insulating layer overlap each other vertically.

Fan-out semiconductor package and electronic device including the same

A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.

Fan-out semiconductor package

A data storage device includes a first memory device having a buffer region including a general region and a host access region, a second memory device, and a controller. The first memory device is directly accessible by the host. The controller controls the first memory device or the second memory device to store data provided from the host. The controller stores the data in the host access region and generates metadata of the data, when the data provided from the host complies with a predetermined condition.

Data storage device and method of operating the same

An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.

Electronic component package having stress alleviation structure

A fan-out semiconductor package includes a first connection member having a through hole, a semiconductor chip in the through hole, having an active surface with a connection pad and an inactive surface on an opposing side. An encapsulant encapsulates at least a portion of the first connection member and the semiconductor chip. A second connection member is on the first connection member and the semiconductor chip. The first connection member and the second connection member each include a redistribution layer electrically connected to a connection pad of the semiconductor chip. The interface between the second connection member and the encapsulant is located on a different level from the level of the interface between the second connection member and a redistribution layer of the first connection member or the level of the interface between the second connection member and a connection pad of the semiconductor chip.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the first semiconductor chip, and the connection pads of the second semiconductor chip are electrically connected to the redistribution layer of the first interconnection member by wires.

A fan-out semiconductor package and an electronic device including the same are provided. The fan-out semiconductor package includes a semiconductor chip; an interconnection member electrically connected to the semiconductor chip and having a connection terminal pad; and a passivation layer disposed at one side of the interconnection member and having an opening part opening a portion of the connection terminal pad. Distances from a center of the connection terminal pad to at least two points of an edge thereof are different from each other.

An electronic component package includes a frame containing a metal or ceramic based material and having a through-hole, an electronic component disposed in the through-hole, an insulating part at least covering upper portions of the frame and the electronic component, a bonding part at least partially disposed between the frame and the insulating part, and a redistribution part disposed at one side of the frame and the electronic component.

Electronic component package and package-on-package structure including the same

An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a through hole accommodating the electronic component, an adhesive layer bonding the wiring part and the frame to each other, and an encapsulant filling at least a portion of the through hole.

Growing community of inventors

Suwon-si, South Korea

Sung Won Jeong