Samsung Electronics Co., Ltd.

Sung-whan Seo

Young-sun Min

Vivek Venkata Kalluru

Bilal Ahmad Janjua

Tae-hong Kwon

Ki-won Kim

Jun-Gyu Lee

Sang-Wan Nam

Won-Tae Kim

Hi-Choon Lee

Tae-hyun Kim

Venkataramana Gangasani

A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Charge pump and memory device including the same

A non-volatile memory device includes a memory cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad; a substrate in the memory cell region; a memory cell array in the memory cell region comprising a plurality of gate conductive layers stacked on the substrate and a plurality of pillars penetrating through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the substrate, wherein at least one of the plurality of gate conductive layers is a ground select line; a control logic circuit in the peripheral circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit in the peripheral circuit configured to, in response to the erase enable signal, output a substrate bias voltage at a first target level to the substrate from a first time to a second time after the first time during a first delay period and, after the first delay period gradually increase a level of the substrate bias voltage to an erase voltage having a higher level than the first target level; and a row decoder in the peripheral circuit configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay period.

Non-volatile memory device and method of erasing the same

A non-volatile memory device includes a substrate; a memory cell array on the substrate; a control logic circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit configured to, in response to the erase enable signal, output a first target voltage to the substrate as a substrate bias voltage during a first delay time and, after the first delay time, output the substrate bias voltage to the substrate while gradually increasing a level of the substrate bias voltage to that of an erase voltage having a higher level than the first target voltage; and a row decoder configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay time.

A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage.

Clock signal generation device and memory device including the same

A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.

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Hwaseong-si, South Korea

Sung-whan Seo