Samsung Electronics Co., Ltd.

Sung-Un Kwon

Jae-Seung Hwang

Jung-Woo Seo

Jun-Kyum Kim

Yong-Sun Ko

Jun Hyuk Seo

Doo-Hwan Park

Yong-Hwan Ryu

Kyoung-Ha Eom

Ik-Soo Kim

Byoung-Jae Bae

Dong-Hyun Im

Sang-sup Jeong

Gyu-Hwan Oh

Chul-Ho Shin

Sung-Lae Cho

Young-Soo Lim

Eun-Young Kang

Dong-Hyun Kim

Jae-Goo Lee

Yoo-Sang Hwang

Eun-Jung Kim

Jun-Soo Bae

Yong-Ho Ha

Hyeong-sun Hong

Jeong-Hee Park

Yong-kwan Kim

Sang-Joon Park

Joon-Sang Park

Yun-seung Kang

Kwang-Ho Park

Nam-Jung Kang

Hyun-Suk Kwon

Min-Chul Chae

Kyu-Man Hwang

Myung-jin Kang

Woo-Jin Cho

Young-Sik Seo

A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Semiconductor devices

Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes

Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes

In a method of manufacturing a semiconductor device, sacrificial layer patterns extending in a first direction are formed on an etch target layer. Preliminary mask patterns are formed on opposite sidewall surfaces of each of the sacrificial layer patterns. A filling layer is formed to fill a space between the preliminary mask patterns. Upper portions of the preliminary mask patterns are etched to form a plurality of mask patterns. Each of the mask patterns is symmetric with respect to a plane passing a center point of each of the mask patterns in a second direction substantially perpendicular to the first direction and extending in the first direction. The sacrificial layer patterns and the filling layer are removed. The etch target layer is etched using the mask patterns as an etching mask to form a plurality of target layer patterns.

Methods of manufacturing semiconductor devices

Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes and method of manufacturing the same

A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Method of forming semiconductor device having self-aligned plug

A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

Phase change memory devices and methods of manufacturing the same

A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.

Method of fabricating semiconductor device

Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH) gas. The etching object layer includes a magnetic material or a phase change material.

Methods of forming pattern structures and methods of manufacturing semiconductor devices using the same

A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.

Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current

A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.

Semiconductor device having contact barrier and method of manufacturing the same

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Jeonju-si, South Korea

Sung-Un Kwon