Samsung Electronics Co., Ltd.

Sung-Taeg Kang

Jeong-Uk Han

Bo-Young Seo

Hee-Seog Jeon

Seung-Beom Yoon

Sung-Woo Park

Ji-hoon Park

Hyok-Ki Kwon

Seong-Gyun Kim

Seung Beom Yoon

Hee Seog Jeon

Chang-Hun Lee

Sang-Su Kim

Byung-Gook Park

Yong-kyu Lee

In-Wook Cho

Hyun-Khe Yoo

Seung-Jin Yang

Yong-Suk Choi

Jeong-Hwan Yang

Jong-Duk Lee

Young-Sam Park

Seung-Gyun Kim

Jung-Wook Han

Bo Young Seo

Yong Tae Kim

Sang-Woo Kang

Jeong-uk Han

BoYoung Seo

Soeng-gyun Kim

In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

Method of fabricating non-volatile flash memory device having at least two different channel concentrations

There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Semiconductor device and method of forming the same

Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Split gate non-volatile memory devices and methods of forming the same

A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

Nonvolatile memory devices and methods of fabricating the same

A nonvolatile semiconductor device includes a pair of multi-bit nonvolatile memory unit cells. Each unit cell includes a grid type semiconductor body in which a plurality of parallel semiconductor bodies extend in a first direction and a plurality of parallel semiconductor bodies extend in a second direction perpendicular to the first direction, a channel region formed in a partial region of the semiconductor body along circumferences of the semiconductor bodies that extend in the first direction, a charge storage region formed on the channel region, a plurality of control gates, which are formed on the charge storage region and wherein each of the plurality of control gates is adapted to receive separate control voltages. Each unit cell further includes source and drain regions aligned on both sides of the plurality of control gates and formed in the semiconductor bodies, wherein the pair of unit cells share the source region, and the source region is formed at a cross point of the grid.

Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same

A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.

Nonvolatile memory device

A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.

Nonvolatile semiconductor device and method of fabricating the same

A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

Twin-ONO-type SONOS memory

A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

EEPROM device having first and second doped regions that increase an effective channel length

A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.

Methods of forming split-gate non-volatile memory devices

Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same

Split gate non-volatile memory devices and methods of forming same

A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

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Seoul, South Korea

Sung-Taeg Kang