Amkor Technology, Inc.

Samsung Electronics Co., Ltd.

Ajou University Industry-Academic Cooperation Foundation

Ewha University-Industry Collaboration Foundation

Sung Su Park

Choon Heung Lee

Sang Jae Jang

Jong Sik Paek

Andrew Zhenwen Chang

Chul Woo Park

Suk Gu Ko

Sung Soon Park

Jung Gi Jin

Jong Won Park

Sun Young Kim

Se Woong Cha

Yoon Jun Lee

Tae Kyung Hwang

Chang Won Ryu

Yong Joo Park

Seok Bong Kim

Soo Hyun Jho

Young Hoon Eom

Jin Young Kim

Young Ho Kim

Jae Ho Kim

Seon Goo Lee

Seong Min Seo

Gwang Hwan Lee

Sang Mok Lee

Eun Sook Sohn

Sun Goo Lee

So Hyun Kim

Ho Cheol Jang

Man Jeong Paik

Geetika Phukan

Kyung Han Ryu

Youn Sang Kim

Seong Won Nam

Sang Mi Hyun

Seok Hyun Choi

Ki Ryung Choi

Seo Gyun Kim

Woo Young Shim

Duc Toan Nguyen

Jin Seok Kang

Kang Mu Lee

Jeom Soon Shim

Tae-Hwan Shin

Tae Gil Eum

Eun Seok Im

Jeong Gi Jin

Andrew Andrew Chang

Soo Hyn Jho

An electronic apparatus and a method of outputting content of the electronic apparatus outputs a synchronized content to a display apparatus and a projection-type display apparatus and a method of outputting a content of the electronic apparatus. The electronic apparatus includes an input/output unit connected with a display apparatus and a projection-type display apparatus, and a control unit configured to control the input/output unit, wherein the control unit outputs a synchronized content to the display apparatus and the projection-type display apparatus through the input/output unit.

Electronic apparatus and method for outputting content

Provided are an electronic device and a content output method of the same. Synchronized content is output to a large format display (LFD) and a small format display (SFD). Content synchronized in correspondence with a user's proximity and/or touch is output to the LFD and the SFD.

Multi-display system, electronic device, and content output method

Disclosed is a biomarker composition for diagnosing the toxicity of nanoparticles, which shows a change in expression by exposure to the nanoparticles, the biomarker composition comprising at least one gene selected from the group consisting of aldehyde dehydrogenase, glutamic-pyruvate transaminase, glutamate dehydrogenase, glutamicoxaloacetic transaminase, glutamic acid decarboxylase and glutamate-ammonia ligase, and to a method for evaluating the toxicity of nanoparticles using the same. The biomarker is a gene marker having a high correlation with the toxicity of nanoparticles, and the use of the biomarker can determine whether nanoparticles have toxicity, with high detection sensitivity. Also, the method is useful in monitoring or evaluating the toxicity of nanoparticles by analyzing factors having a high correlation with toxicity of nanoparticles. Furthermore, the method can be effectively used as a tool for studying various diseases caused by exposure to nanoparticles or evaluating the effects of nanoparticles on health.

Biomarker for diagnosing toxicity of nanoparticles and method for evaluating toxicity of nanoparticles using the same

A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

Semiconductor device and manufacturing method thereof

An apparatus for evaluating sound quality and a method thereof may include generating an original sound, measuring a test sound generated from a subject of sound quality evaluation, analyzing a signal of the test sound measured according to a time domain, generating a plurality delay signals that are delayed from the signal of the time domain by one period, determining a degree of matching by matching the signal of the time domain to each delay signal, determining whether a white nose is occurred based on the degree of matching, and outputting the status of the white noise on the subject of the sound evaluation. The signal of the test sound may be analyzed according to a frequency domain, and a degree of occurrence of buzz and rattle is determined based on a fundamental frequency of the frequency domain and a plurality of Harmonics corresponding to the frequency domain.

Sound quality evaluation apparatus and method thereof

A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.

Wafer level chip scale package and method of fabricating wafer level chip scale package

Semiconductor device having redistribution layer

A micro- or nano-fluidic chip fabricated with a Norland Optical Adhesive (NOA), an acrylated polyurethane-based UV-polymerizable optical adhesive. The micro- or nano-fluidic chip has sequentially an inlet, a channel, and an outlet. The channel has a pillar in the region of the outlet to prevent beads from flowing out, and the surface of the channels in the micro- or nano-fluidic chip is hydrophilic, which generates spontaneous flow in the channels by a capillary force without any extra external pumping.

Micro- or nano-fluidic chip fabricated with Norland Optical Adhesive and bioanalysis platform produced by using the same

Disclosed is a semiconductor package. The semiconductor package is configured to form a plurality of through holes for forming a through silicon via at once using a sawing device used for wafer sawing instead of a separate laser drilling equipment or a deep reactive ion etching (DRIE) equipment. Accordingly, the semiconductor package saves fabricating time and increases fabrication yield, saves costs for a laser drilling equipment or a DRIE equipment, and prevents various defects generated in an inner portion of a through hole in the case of using the laser drilling equipment or the DRIE equipment.

Semiconductor package having through holes

A memory card comprising a substrate having opposed top and bottom surfaces and a plurality of terminals disposed on the bottom surface thereof. Mounted to the top surface of the substrate is at least one component which is itself electrically connected to the terminals of the substrate. Formed on the bottom surface of the substrate is a first encapsulation part. Formed on the top surface of the substrate is a second encapsulation part which encapsulates the component mounted thereto.

Double mold memory card and its manufacturing method

Disclosed are a wafer level chip scale package and a method for manufacturing the same. An RDL is formed on a semiconductor die through a sputtering process, and a UBM is formed on the RDL through an electroplating process by using the RDL as a seed layer. Thus, the RDL sputtering, UBM electroplating, RDL etching and leakage descum processes are carried out only one time, thereby simplifying the structure and manufacturing processes of the package. Since a copper layer of the RDL is formed with a relatively large thickness through the sputtering process, current density is uniformly distributed during the electroplating process, so it is possible to uniformly form the thickness of the UBM by using pure nickel.

Wafer level chip scale package and manufacturing method for the same

Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; an electronic device placed on the first coating layer; a connection member for electrically connecting the electronic device and the redistribution layer; a conductive post formed on the redistribution layer with a predetermined thickness; a second coating layer for enclosing the first coating layer, the redistribution layer, the electronic device, the connection member, and the conductive post; and a solder ball thermally bonded to the conductive post while protruding to the exterior of the second coating layer. This construction makes it easy to manufacture stacked packages and chip scale packages in a wafer level.

Wafer level chip scale package

A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, at least one test pad disposed on the upper circuit board surface, and a conductive pattern disposed on the lower circuit board surface and electrically connected to the test pad. Electrically connected to the conductive pattern of the circuit board is a leadframe which includes a plurality of leads, each of the leads having a signal pad portion. At least one electronic circuit element is attached to the lower circuit board surface and electrically connected to the leadframe and to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board, the leadframe and the electronic circuit element such that the test pad of the circuit board is exposed in an upper body surface of the body, and the signal pad portions of the leads of the leadframe are exposed in a lower body surface of the body.

Memory card and its manufacturing method

A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which has opposed, generally planar first and second contact surfaces. An inner body partially encapsulates the die paddle and the contacts, the first contact surface of each of the contacts and the first die paddle surface of the die paddle being exposed in and substantially flush with a generally planar first inner body surface of the inner body. The inner body further defines a generally planar second inner body surface which is disposed in opposed relation to the first inner body surface, the second contact surface of each of the contacts being exposed in the second inner body surface. At least one electronic circuit element is attached to the first die paddle surface and electrically connected to at least one of the contacts. An outer body partially encapsulates the inner body such that the first die paddle surface, the first contact surface of each of the contacts, the first inner body surface and the electronic circuit element are covered by the outer body, with the second inner body surface and hence the second contact surface of each of the contacts not being covered by the outer body and thus exposed.

Growing community of inventors

Seoul, South Korea

Sung Su Park